An improved communication scheme for non-HOL-blocking wireless NoC

Abstract As the wireless interface often requires handling numbers of data simultaneously in wireless network-on-chip, it potentially causes data congestions. The degradation of wireless data transfer can tremendously reduce the efficiency of the network communication. In this paper, virtual output queuing (VOQ) technique has been used to eliminate the head-of-line blocking issue. Moreover, a novel and effective communication scheme has also been introduced to alleviate the traffic load in wireless nodes and hence improving the efficiency of wireless communication. Simulation results indicate that our proposed architecture is advantageous in various aspects including the transfer latency, network throughput and energy consumption.

[1]  An-Yeu Wu,et al.  Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems , 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.

[2]  Niraj K. Jha,et al.  Token flow control , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[3]  Luca Benini,et al.  Networks on chip: a new paradigm for systems on chip design , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[4]  P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .

[5]  Y. Tamir,et al.  High-performance multi-queue buffers for VLSI communications switches , 1988, ISCA '88.

[6]  Partha Pratim Pande,et al.  Performance evaluation of wireless networks on chip architectures , 2009, 2009 10th International Symposium on Quality Electronic Design.

[7]  David Blaauw,et al.  A Reliable Routing Architecture and Algorithm for NoCs , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Chifeng Wang,et al.  A Wireless Network-on-Chip Design for Multicore Platforms , 2011, 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing.

[9]  Partha Pratim Pande,et al.  Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges , 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[10]  Yi Wang,et al.  SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip , 2008, IEEE Transactions on Computers.

[11]  Srinivasan Murali,et al.  A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[12]  Christopher Batten,et al.  Silicon-photonic clos networks for global on-chip communication , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[13]  Radu Marculescu,et al.  "It's a small world after all": NoC performance optimization via long-range link insertion , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[16]  Emile H. L. Aarts,et al.  Simulated Annealing: Theory and Applications , 1987, Mathematics and Its Applications.

[17]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[18]  Christof Teuscher,et al.  Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems , 2011, IEEE Transactions on Computers.

[19]  Jason Cong,et al.  A scalable micro wireless interconnect structure for CMPs , 2009, MobiCom '09.

[20]  Zhen Wang,et al.  Flow Control Mechanism for Wireless Network-on-Chip , 2013, 2013 10th International Conference on Information Technology: New Generations.

[21]  P. Cochat,et al.  Et al , 2008, Archives de pediatrie : organe officiel de la Societe francaise de pediatrie.

[22]  Chih-Ming Hung,et al.  Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters , 2002, IEEE J. Solid State Circuits.

[23]  Akif Ali,et al.  Near-optimal worst-case throughput routing for two-dimensional mesh networks , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[24]  Jason Cong,et al.  CMP network-on-chip overlaid with multi-band RF-interconnect , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[25]  Partha Pratim Pande,et al.  Performance evaluation of wireless NoCs in presence of irregular network routing strategies , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[26]  Radu Marculescu,et al.  Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs , 2016, IEEE Transactions on Computers.

[27]  Partha Pratim Pande,et al.  High performance and energy efficient wireless NoC-enabled multicore architectures for graph analytics , 2015, 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES).

[28]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について - シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について - , 2004 .

[29]  Salvatore Monteleone,et al.  Noxim: An open, extensible and cycle-accurate network on chip simulator , 2015, 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

[30]  K. Kempa,et al.  Carbon Nanotubes as Optical Antennae , 2007 .

[31]  Partha Pratim Pande,et al.  Performance Evaluation of Congestion-Aware Routing with DVFS on a Millimeter-Wave Small-World Wireless NoC , 2014, JETC.

[32]  Shigeru Oyanagi,et al.  A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip Networks , 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

[33]  Partha Pratim Pande,et al.  A wideband body-enabled millimeter-wave transceiver for wireless Network-on-Chip , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).