A low dropout, CMOS regulator with high PSR over wideband frequencies

Modern system-on-chip (SoC) environments are swamped in high frequency noise that is generated by RF and digital circuits and propagated onto supply rails through capacitive coupling. In these systems, linear regulators are used to shield noise-sensitive analog blocks from high frequency fluctuations in the power supply. The paper presents a low dropout regulator that achieves power supply rejection (PSR) better than -40 dB over the entire frequency spectrum. The system has an output voltage of 1.0 V and a maximum current capability of 10 mA. It consists of operational amplifiers (op amps), a bandgap reference, a clock generator, and a charge pump and has been designed and simulated using BSIM3 models of a 0.5 /spl mu/m CMOS process obtained from MOSIS.

[1]  Michel Declercq,et al.  A high-efficiency CMOS voltage doubler , 1998, IEEE J. Solid State Circuits.

[2]  Hannu Tenhunen,et al.  Efficient and accurate modeling of power supply noise on distributed on-chip power networks , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[3]  V. von Kaenel.  A high-speed, low-power clock generator for a microprocessor application , 1998 .

[4]  Mayu Aoki,et al.  A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme , 1999 .

[5]  Willy Sansen,et al.  Power supply rejection ratio in operational transconductance amplifiers , 1990 .

[6]  M. A. Copeland,et al.  Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range , 1984 .

[7]  J. Choma,et al.  A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter , 2001, IEEE J. Solid State Circuits.

[8]  Raminderpal Singh.  Power Supply Noise in Future IC's: A Crystal Ball Reading , 2002 .

[9]  Phillip E Allen,et al.  CMOS Analog Circuit Design , 1987 .

[10]  W. Guggenbuhl,et al.  A general relationship between amplifier parameters, and its application to PSRR improvement , 1991 .

[11]  Dorin Patru,et al.  Power supply noise coupling in a standard voltage reference circuit , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[12]  Gaetano Palumbo,et al.  A detailed analysis of power-supply noise attenuation in bandgap voltage references , 2003 .

[13]  K. Leung,et al.  A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device , 2002, IEEE J. Solid State Circuits.

[14]  Bram Nauta,et al.  Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology , 1998, IEEE J. Solid State Circuits.

[15]  P. Larsson.  Power supply noise in future IC's: a crystal ball reading , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[16]  B. Nauta,et al.  Embedded 5V-to-3.3V voltage regulator for supplying digital ICs in 3.3V CMOS technology , 1997, Proceedings of the 23rd European Solid-State Circuits Conference.

[17]  Gabriel A. Rincón-Mora,et al.  Analysis and design of monolithic, high PSR, linear regulators for SoC applications , 2004, IEEE International SOC Conference, 2004. Proceedings..

[18]  Kaushik Roy,et al.  Estimation of switching noise on power supply lines in deep sub-micron CMOS circuits , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[19]  V. von Kaenel,et al.  A 4-GHz clock system for a high-performance system-on-a-chip design , 2001 .