论文信息 - A 1-V, 3.44-ns, 4.1-mW at 50-MHz, 128-Kb four-way set-associative CMOS cache memory implemented by 1.8V 0.18µm foundry CMOS technology for low-voltage low-power VLSI system applications

A 1-V, 3.44-ns, 4.1-mW at 50-MHz, 128-Kb four-way set-associative CMOS cache memory implemented by 1.8V 0.18µm foundry CMOS technology for low-voltage low-power VLSI system applications

This paper reports a 1-V, 3.44-ns, 4.1-mW at 50MHz, 128- Kb, four-way set-associative CMOS cache memory implemented by TSMC 1.8V 0.18µm foundry CMOS technology for low-voltage low-power VLSI system applications. Owing to the distributed tag sense-amps with a dynamic logic control, the 10-T tag cell with the built-in tag compare capability, and the dynamic pulse generators for realizing read enable signals, a small hit access time, a high hit rate, and low power consumption have been reached. The hit access time of this 128-Kb four-way set-associative CMOS cache memory is 3.44ns at VDD=1V, with power consumption of 4.1-mW at 50MHz.

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