A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS

Interconnect networks, for high-bandwidth energy-efficient core-to-core communication, are key to enabling future tera-scale multi-core processors. Packet-switched 2D mesh networks provide efficient interconnect utilization, low latencies and high throughputs, but suffer from low energy efficiency due to data storage during routing [1–2]. Circuit-switched data transfer achieves both high bandwidth and energy efficiency by eliminating intra-route data storage [3]. An 8×8 mesh circuit-switched network-on-chip, consisting of arbitration logic for 512b data width with 1b data interconnect, is fabricated in 45nm high-к metal-gate CMOS [4]. Scaling data width measurements to 512b, the circuits achieve 560Gb/s/W energy efficiency, 4.1Tb/s bisection bandwidth, and 11ns diagonal corner-to-corner fall-through latency. Reconfigurable router circuits allow dynamic optimization of both circuit-switched channel-queue depth and the ratio of arbitration vs. data transfer rates based on traffic patterns. Pipelined arbitration phases with packet-switched channel allocation circuits, dual-supply optimization of data transfer power and proximity-based streaming circuits enable: i) 2.64Tb/s maximum throughput for random 512b transmissions measured at 1.1V, 50°C, ii) 87% increased throughput from channel queuing, iii) 6.43Tb/s scalable performance with streaming traffic at energy efficiency of 0.91Tb/s/W, iv) 4.73W total network power at 74mW per router with ≪17% arbitration overhead, v) traffic-dependent network power consumption scalable down to 1.35W at 21mW per router, vi) 28% power savings through dual-supply optimization at iso-throughput, and vii) low-voltage energy efficiency of 1.51Tb/s/W measured at 550mV, 50°C.