Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges
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[1] J.G. Fossum,et al. Analysis and control of hysteresis in PD/SOI CMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
[2] Ching-Te Chuang,et al. Scaling planar silicon devices , 2004, IEEE Circuits and Devices Magazine.
[3] Rajiv V. Joshi,et al. A novel technique for steady state analysis for VLSI circuits in partially depleted SOI , 2004, 17th International Conference on VLSI Design. Proceedings..
[4] R.P. Jindal. Noise associated with distributed resistance of MOSFET gate structures in integrated circuits , 1984, IEEE Transactions on Electron Devices.
[5] Alvin B. Phillips. Transistor engineering and introduction to integrated semiconductor circuits , 1962 .
[6] Pin Su,et al. A body-contact SOI MOSFET model for circuit simulation , 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).
[7] Zhi-Yuan Wu,et al. History-effect-conscious SPICE model extraction for PD-SOI technology , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).
[8] M.B. Ketchen,et al. Technique for rapid, in-line characterization of switching history in partially depleted SOI technologies , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).
[9] Xin Li,et al. PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs , 2007, 2007 IEEE Custom Integrated Circuits Conference.
[10] A. Mercha,et al. "Linear kink effect" induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETS , 2003 .
[11] J. Watts. Enhancing Productivity by Continuously Improving Standard Compact Models , 2006, IEEE Custom Integrated Circuits Conference 2006.
[12] P. Flatresse,et al. A new and fast method to compute steady state in PD-SOI circuits and its application to standard cells library characterization , 2003, 2003 IEEE International Conference on SOI.
[13] A. Wei,et al. Bounding the severity of hysteretic transient effects in partially-depleted SOI CMOS , 1996, 1996 IEEE International SOI Conference Proceedings.
[14] Gerard Merckel,et al. A re-examination of the physics of multiplication-induced breakdown in MOSFETs , 1989, International Technical Digest on Electron Devices Meeting.
[15] G. O. Workman,et al. A comparative analysis of the dynamic behavior of BTG/SOI MOSFETs and circuits with distributed body resistance , 1998 .
[16] S. Chu,et al. Floating body effects in partially-depleted SOI CMOS circuits , 1996, ISLPED.
[17] Ching-Te Chuang,et al. Hysteresis effect in pass-transistor-based, partially depleted SOI CMOS circuits , 2000, IEEE Journal of Solid-State Circuits.
[18] I. Eisele,et al. Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFETs , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
[19] C. C. Nash. Transistor engineering and introduction to integrated semiconductor circuits , 1963 .
[20] J. Roychowdhury. Analyzing circuits with widely separated time scales using numerical PDE methods , 2001 .
[21] Pin Su,et al. Studying the impact of gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD , 2002, Proceedings International Symposium on Quality Electronic Design.
[22] Ching-Te Chuang,et al. SOI for digital CMOS VLSI: design considerations and advances , 1998, Proc. IEEE.
[23] Tran Ly,et al. Extraction of Self-Heating Free I-V Curves Including the Substrate Current of PD SOI MOSFETs , 2007, 2007 IEEE International Conference on Microelectronic Test Structures.
[24] Ching-Te Chuang,et al. Floating-body effects in partially depleted SOI CMOS circuits , 1997 .
[25] K. S. Kundert,et al. Introduction to RF simulation and its application , 1998, Proceedings of the 1998 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.98CH36198).
[26] W. Clark,et al. SOI 90-nm ring oscillator sub-ps model-hardware correlation and parasitic-aware optimization leading to 1.94-ps switching delay , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[27] Judy Xilin An,et al. Impact of Gate Induced Drain Leakage and Impact Ionization Currents on Hysteresis Modeling of PD SOI Circuits , 2007 .
[28] S. Narasimha,et al. High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography , 2006, 2006 International Electron Devices Meeting.
[29] S. Laux,et al. Monte Carlo study of sub-band-gap impact ionization in small silicon field-effect transistors , 1995, Proceedings of International Electron Devices Meeting.
[30] David Anderson. Comparison of Spice Vs. Harmonic Balance Simulations , 2000, 55th ARFTG Conference Digest.
[31] Qiang Chen,et al. An A Priori Hysteresis Modeling Methodology for Improved Efficiency and Model Accuracy in Advanced PD SOI Technologies , 2005 .
[32] D.H. Allen,et al. A 0.2 /spl mu/m 1.8 V SOI 550 MHz 64 b PowerPC microprocesser with copper interconnects , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
[33] Edward J. Nowak,et al. Predicting the SOI History Effect Using Compact Models , 2004 .
[34] Ching-Te Chuang,et al. Hysteresis effect in pass-transistor based partially-depleted SOI CMOS circuits , 1998, 1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199).