Circuit level prediction of device performance degradation due to negative bias temperature stress

Abstract A circuit level methodology for predicting performance degradations due to negative bias temperature stress is developed in this paper. Degradation mechanism is discussed based on experimental observations. Then, models that consist of a threshold voltage shift and a drain current reduction are developed based on the degradation mechanism. The developed models are implemented into a compact MOSFET model so that we can directly link the local degradation of pMOSFETs’ electrical characteristics to the total circuit performances. The validity of the developed models is confirmed by the good agreement in simulated and measured results of I – V characteristics of pMOSFET in all the transistor working region before and after negative bias temperature stress. Then, circuit performance prediction is carried out for the stressed 199-stage ring oscillator on its waveform and oscillation frequency. Excellent agreements between the experimental results and predicted results are obtained.

[1]  M. Agostinelli,et al.  PMOS NBTI-induced circuit mismatch in advanced technologies , 2004 .

[2]  S. Rauch The statistics of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in pMOSFETs , 2002 .

[3]  M.A. Alam,et al.  A critical examination of the mechanics of dynamic NBTI for PMOSFETs , 2003, IEEE International Electron Devices Meeting 2003.

[4]  E. Murakami,et al.  Modeling of NBTI degradation and its impact on electric field dependence of the lifetime , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[5]  Steve Jacobs,et al.  The impact of PMOST bias-temperature degradation on logic circuit reliability performance , 2005, Microelectron. Reliab..

[6]  Makoto Hirayama,et al.  Dielectric breakdown caused by hole-induced-defect in thin SiO2 films , 1997 .

[7]  D. Schroder,et al.  Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing , 2003 .

[8]  M.A. Alam,et al.  Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs , 2004, IEEE Transactions on Electron Devices.

[9]  K. Watanabe,et al.  Accurate circuit performance prediction model and lifetime prediction method of nbt stressed devices for highly reliable ulsi circuits , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[10]  M. Houssa,et al.  Modelling negative bias temperature instabilities in advanced p-MOSFETs , 2005, Microelectron. Reliab..

[11]  F. Stern,et al.  Electronic properties of two-dimensional systems , 1982 .

[12]  Karl Goser,et al.  Effects of inhomogeneous negative bias temperature stress on p-channel MOSFETs of analog and RF circuits , 2005, Microelectron. Reliab..

[13]  V. Huard,et al.  Hole trapping effect on methodology for DC and AC negative bias temperature instability measurements in PMOS transistors , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[14]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[15]  S. John,et al.  NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.

[16]  M. Khare,et al.  Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[17]  A. Toriumi,et al.  NBTI mechanism in ultra-thin gate dielectric - nitrogen-originated mechanism in SiON , 2002, Digest. International Electron Devices Meeting,.

[18]  Shimpei Tsujikawa,et al.  Positive charge generation due to species of hydrogen during NBTI phenomenon in pMOSFETs with ultra-thin SiON gate dielectrics , 2005, Microelectron. Reliab..

[19]  K. Yamaguchi,et al.  The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[20]  Massimo V. Fischetti,et al.  Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks , 2003 .

[21]  V. Huard,et al.  On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET's , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[22]  Shigeo Ogawa,et al.  Interface‐trap generation at ultrathin SiO2 (4–6 nm)‐Si interfaces during negative‐bias temperature aging , 1995 .

[23]  Ogawa,et al.  Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO2 interface. , 1995, Physical review. B, Condensed matter.

[24]  B.C. Paul,et al.  Impact of NBTI on the temporal performance degradation of digital circuits , 2005, IEEE Electron Device Letters.

[25]  C. Hu,et al.  A model for hot-electron-induced MOSFET linear-current degradation based on mobility reduction due to interface-state generation , 1991 .

[26]  D. Kwong,et al.  Dynamic NBTI of PMOS transistors and its impact on device lifetime , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[27]  Rihito Kuroda,et al.  Examination of degradation mechanism due to negative bias temperature stress from a perspective of hole energy for accurate lifetime prediction , 2007, Microelectron. Reliab..