Stochastic Modeling of Hybrid Cache Systems

In recent years, there is an increasing demand of big memory systems so to perform large scale data analytics. Since DRAM memories are expensive, some researchers are suggesting to use other memory systems such as non-volatile memory (NVM) technology to build large-memory computing systems. However, whether the NVM technology can be a viable alternative (either economically and technically) to DRAM remains an open question. To answer this question, it is important to consider how to design a memory system from a "system perspective",that is, incorporating different performance characteristics andprice ratios from hybrid memory devices. This paper presents an analytical model of a "hybrid page cache system" so to understand the diverse design space and performance impact of a hybrid cache system. We consider (1) various architectural choices, (2) design strategies, and (3) configuration of different memory devices. Using this model, we provide guidelines on how to design hybrid page cache to reach a good trade-off between high system throughput (in I/O per sec or IOPS) and fast cache reactivity which is defined by the time to fill the cache. We also show how one can configure the DRAM capacity and NVM capacity under a fixed budget. We pick PCM as an example for NVM and conduct numerical analysis. Our analysis indicates that incorporating PCM in a page cache system significantly improves the system performance, and it also shows larger benefit to allocate more PCM in page cache in some cases. Besides, for the common setting of performance-price ratio of PCM, "flat architecture" offers as a better choice, but "layered architecture" outperforms if PCM write performance can be significantly improved in the future.

[1]  Ki-Woong Park,et al.  OPAMP: Evaluation Framework for Optimal Page Allocation of Hybrid Main Memory Architecture , 2012, 2012 IEEE 18th International Conference on Parallel and Distributed Systems.

[2]  Wei-Che Tseng,et al.  Software enabled wear-leveling for hybrid PCM main memory on embedded systems , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[3]  George Kingsley Zipf,et al.  Relative Frequency as a Determinant of Phonetic Change , 1930 .

[4]  Eunji Lee,et al.  Eliminating Periodic Flush Overhead of File I/O with Non-Volatile Buffer Cache , 2016, IEEE Transactions on Computers.

[5]  Trevor N. Mudge,et al.  Improving NAND Flash Based Disk Caches , 2008, 2008 International Symposium on Computer Architecture.

[6]  Benny Van Houdt,et al.  Transient and steady-state regime of a family of list-based cache replacement algorithms , 2015, Queueing Systems.

[7]  Daniel Pierre Bovet,et al.  Understanding the Linux Kernel , 2000 .

[8]  Shih-Hung Chen,et al.  Phase-change random access memory: A scalable technology , 2008, IBM J. Res. Dev..

[9]  K QureshiMoinuddin,et al.  Scalable high performance main memory system using phase-change memory technology , 2009 .

[10]  Rachata Ausavarungnirun,et al.  Row buffer locality aware caching policies for hybrid memories , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

[11]  Jean-Yves Le Boudec,et al.  The stationary behaviour of fluid limits of reversible processes is concentrated on stationary points , 2010, Networks Heterog. Media.

[12]  Vijayalakshmi Srinivasan,et al.  Scalable high performance main memory system using phase-change memory technology , 2009, ISCA '09.

[13]  Onur Mutlu,et al.  Architecting phase change memory as a scalable dram alternative , 2009, ISCA '09.

[14]  Margo I. Seltzer,et al.  Flash Caching on the Storage Client , 2013, USENIX Annual Technical Conference.

[15]  Hyojun Kim,et al.  Evaluating Phase Change Memory for Enterprise Storage Systems: A Study of Caching and Tiering Approaches , 2014, TOS.

[16]  Yiran Chen,et al.  Emerging non-volatile memories: Opportunities and challenges , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[17]  Li Fan,et al.  Web caching and Zipf-like distributions: evidence and implications , 1999, IEEE INFOCOM '99. Conference on Computer Communications. Proceedings. Eighteenth Annual Joint Conference of the IEEE Computer and Communications Societies. The Future is Now (Cat. No.99CH36320).

[18]  Bruce Jacob,et al.  DRAMSim2: A Cycle Accurate Memory System Simulator , 2011, IEEE Computer Architecture Letters.

[19]  Roy D. Yates,et al.  A Framework for Uplink Power Control in Cellular Radio Systems , 1995, IEEE J. Sel. Areas Commun..

[20]  Tajana Simunic,et al.  PDRAM: A hybrid PRAM and DRAM main memory system , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[21]  GastNicolas,et al.  Transient and steady-state regime of a family of list-based cache replacement algorithms , 2016 .

[22]  Trevor N. Mudge,et al.  FlashCache: a NAND flash memory file cache for low power web servers , 2006, CASES '06.

[23]  G. Zipf,et al.  Relative Frequency as a Determinant of Phonetic Change , 1930 .

[24]  Weimin Zheng,et al.  FastScale: Accelerate RAID Scaling by Minimizing Data Migration , 2011, FAST.