Design of high performance 8-bit Vedic multiplier

Multiplier is an essential functional block of a microprocessor because multiplication is needed to be performed repeatedly in almost all scientific calculations. Therefore, design of fast and low power binary multiplier is very important particularly for Digital Signal Processors. This paper describes a design of fast and low power 8-bit multiplier architecture which implements Urdhva-tiryakbyham sutra of Vedic method of multiplication. The multiplier is designed in 180nm technology using cadence EDA tool and simulated using spectre simulator and found to be working correctly and results have been compared foe pre-layout and post-layout analysis. It is shown that implementation of multiplier using the Vedic sutra leads to a very compact layout leading to significantly smaller Silicon area and very small contribution of interconnections to the overall propagation delay of the multiplier. The performance of the proposed multiplier has been compared with those of other multipliers reported in literature.

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