Reconfigurable architectures for parallel execution of image processing tasks

Reconfigurable computers are becoming third, after general purpose processors and digital signal processors, programmable computing systems. In the present paper, a new definition of parallelism adequate for fine-grain parallel systems is introduced. Computing power requirements for high definition, real-time vision system are discussed. A survey of reconfigurable solutions for image processing and the latest research work carried on at the AGH Laboratory of Biocybernetics are presented.

[1]  Gerald Estrin,et al.  Organization of Computer Systems-the Fixed Plus Variable Structure Computer , 1899 .

[2]  Marek Gorgon,et al.  Hardware-based image processing library for Virtex FPGA , 2000, SPIE Optics East.

[3]  Francisco Ibarra,et al.  Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems , 2001, FPL.

[4]  Sergio Cuenca-Asensi,et al.  Accelerating Statistical Texture Analysis with an FPGA-DSP Hybrid Architecture , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[5]  Reiner W. Hartenstein Reconfigurable computing: a new business model-and its impact on SoC design , 2001, Proceedings Euromicro Symposium on Digital Systems Design.

[6]  Danny Crookes,et al.  High Level Programming for FPGA Based Image and Video Processing Using Hardware Skeletons , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[7]  Karl S. Hemmert,et al.  An Application-Specific Compiler for High-Speed Binary Image Morphology , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[8]  Abbes Amira,et al.  Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing , 2002, FPL.

[9]  Takashi Yokota,et al.  A scalable FPGA-based custom computing machine for a medical image processing , 2002, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[10]  Wayne Luk,et al.  Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer , 2002, FPL.

[11]  Klaus Buchenrieder,et al.  Integration of Reconfigurable Hardware into System-Level Design , 2002, FPL.

[12]  Ernest Jamro,et al.  Dynamic Constant Coefficient Convolvers Implemented in FPGAs , 2002, FPL.

[13]  Marek Gorgon,et al.  Handel-C Implementation of Handwritten Digits Recognition , 2003 .

[14]  Heather M. Quinn,et al.  Runtime assignment of reconfigurable hardware components for image processing pipelines , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

[15]  Peter Lee,et al.  An FPGA implementation of a flexible, parallel image processing architecture suitable for embedded vision systems , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[16]  Wayne Luk,et al.  SoftSONIC: A Customisable Modular Platform for Video Applications , 2004, FPL.

[17]  Christos A. Papachristou,et al.  A reconfigurable SoC architecture and caching scheme for 3D medical image processing , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[18]  Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters , 2004, FPL.

[19]  Wayne Luk,et al.  Methods and Tools for High-Resolution Imaging , 2004, FPL.

[20]  Leslie Sánchez,et al.  FPGA Implementation of Biometric Authentication System Based on Hand Geometry , 2004, FPL.

[21]  Ahmed Bouridane,et al.  An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer , 2004, FPL.

[22]  Shengqi Yang,et al.  Power and performance analysis of motion estimation based on hardware and software realizations , 2005, IEEE Transactions on Computers.

[23]  P. A. Subrahmanyam,et al.  Guest Editors' Introduction: Advances in Configurable Computing , 2005, IEEE Des. Test Comput..

[24]  L. Ridgway Scott,et al.  Scientific Parallel Computing , 2005 .

[25]  Maya Gokhale,et al.  Metropolitan road traffic simulation on FPGAs , 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

[26]  John Wawrzynek,et al.  BEE2: a high-end reconfigurable computing system , 2005, IEEE Design & Test of Computers.

[27]  Marek Gorgon,et al.  Real-time Handel-C based implementation of DV decoder , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[28]  Marek Gorgon,et al.  Neural Network Implementation in Reprogrammable FPGA Devices - An Example for MLP , 2006, ICAISC.

[29]  Sonia Mota,et al.  Highly Paralellized Architecture for Image Motion Estimation , 2006, ARC.

[30]  Marek Gorgon,et al.  Real-Time implementation of motion detection algorithm based on pixelstreams , 2006 .

[31]  Javier Díaz,et al.  General Purpose Real-Time Image Segmentation System , 2006, ARC.