Design of vedic multiplier using adiabatic logic

A multiplier is a vital element in many arithmetic and logical units, digital signal processing and communication system. Therefore speed, area and power consumptions are the critical parameters for the designing of multiplier circuits. This paper presents a comparative study of binary Vedic multiplier using CMOS, PFAL and ECRL. The design is based on ancient Indian Vedic mathematics and the low power charge recovery logic. In Vedic multiplication, generation of partial sums and products is performed in single step so this along with adiabatic approach helps in realizing the high speed and low power operation of the binary Vedic multiplier design. The designs are simulated on Cadence Virtuoso Tool using UMC 180 nm CMOS technology. Simulation results show PFAL is the best technology as compared to CMOS, ECRL design for low power implementation of Vedic multiplier.

[1]  Charu Madhu,et al.  High speed vedic multiplier designs-A review , 2014, 2014 Recent Advances in Engineering and Computational Sciences (RAECS).

[2]  Manoj Sharma,et al.  Design of basic gates using ECRL and PFAL , 2013, 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

[3]  V. S. Kanchana Bhaaskaran,et al.  Low power vedic multiplier using energy recovery logic , 2014, 2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

[4]  Doris Schmitt-Landsiedel,et al.  Improving the positive feedback adiabatic logic familiy , 2005 .

[5]  Peter Kulchyski.  and , 2015 .

[6]  Philip Teichmann.  Adiabatic Logic: Future Trend and System Level Perspective , 2011 .

[7]  Roberto Saletti,et al.  A comparison of some circuit schemes for semi-reversible adiabatic logic , 2002 .

[8]  Chan Mo Kim,et al.  Multiplier design based on ancient Indian Vedic Mathematics , 2008, 2008 International SoC Design Conference.

[9]  Deog-Kyoon Jeong,et al.  An efficient charge recovery logic circuit , 1996, IEEE J. Solid State Circuits.

[10]  S. Jain,et al.  Novel transistor level realization of ultra low power high-speed adiabatic Vedic multiplier , 2013, 2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s).