Performances improvement of FPGA using novel multilevel hierarchical interconnection structure

This paper presents a new multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: a predictible downward network based on the Butterfly-Fat-Tree topology, and an upward network using hierarchy. Studies based on the Rent's Rule show that wiring and switch requirements in the MFPGA grow slower than in traditional topologies. New tools are developed to place and route several benchmark circuits on this architecture. Experimental results based on the MCNC benchmarks show that MFPGA can implement circuits with an average gain of 40% in total area compared with mesh architecture

[1]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[2]  Yen-Tai Lai,et al.  Hierarchical interconnection structures for field programmable gate arrays , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Charles E. Leiserson,et al.  Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.

[4]  Raphael Rubin,et al.  Design of FPGA interconnect for multilevel metallization , 2003, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  George Varghese,et al.  HSRA: high-speed, hierarchical synchronous reconfigurable array , 1999, FPGA '99.

[6]  Zied Marrakchi,et al.  A new multilevel hierarchical MFPGA and its suitable configuration tools , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[7]  J. Rose,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2000, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Carl Ebeling,et al.  PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[9]  André DeHon,et al.  Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization) , 1999, FPGA '99.

[10]  RoseJonathan,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2004 .

[11]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[12]  Raphael Rubin,et al.  Design of FPGA interconnect for multilevel metallization , 2004, IEEE Trans. Very Large Scale Integr. Syst..

[13]  David M. Lewis,et al.  Routing architectures for hierarchical field programmable gate arrays , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[14]  Roy L. Russo,et al.  On a Pin Versus Block Relationship For Partitions of Logic Graphs , 1971, IEEE Transactions on Computers.

[15]  André DeHon,et al.  Unifying mesh- and tree-based programmable interconnect , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.