CASE: A reliability simulation tool for analog ICs
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Francisco V. Fernández | Montserrat Nafría | R. Castro-López | Javier Martín-Martínez | Rosana Rodríguez | Elisenda Roca | A. Toro-Frias | P. Martín-Lloret
[1] Sani R. Nassif. Technology modeling and characterization beyond the 45nm node , 2008, 2008 Asia and South Pacific Design Automation Conference.
[2] M. Nafría,et al. Probabilistic defect occupancy model for NBTI , 2011, 2011 International Reliability Physics Symposium.
[3] Moonju Cho,et al. Positive and negative bias temperature instability on sub-nanometer eot high-K MOSFETs , 2010, 2010 IEEE International Reliability Physics Symposium.
[4] Samar K. Saha,et al. Compact MOSFET Modeling for Process Variability-Aware VLSI Circuit Design , 2014, IEEE Access.
[5] Georges Gielen,et al. Analog IC Reliability in Nanometer CMOS , 2013 .
[6] T. Grasser. Bias Temperature Instability for Devices and Circuits , 2014 .
[7] Tibor Grasser,et al. Hot Carrier Degradation in Semiconductor Devices , 2015 .
[8] Francisco V. Fernández,et al. Reliability simulation for analog ICs: Goals, solutions, and challenges , 2016, Integr..
[9] Ali Emre Pusane,et al. A deterministic aging simulator and an analog circuit sizing tool robust to aging phenomena , 2015, 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).
[10] Francisco V. Fernández,et al. A size-adaptive time-step algorithm for accurate simulation of aging in analog ICs , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).