Mapping an H.264/AVC decoder onto the ADRES reconfigurable architecture

H.264/AVC video coding standard promises improved coding efficiency compared with other standards such as MPEG-2. However, its computational complexity is also increased significantly. Efficiently mapping H.264/AVC decoder onto a flexible platform presents a big challenge to existing architectures and design methodology. This paper describes the process and results of mapping H.264/AVC decoder onto the ADRES architecture (Mei et al., 2003), which is a flexible coarse-grained reconfigurable architecture template that tightly couples a VLIW processor and a coarse-grained array.