Characterization and modeling of CMOS on-chip coupled interconnects

In this paper, an S-parameter measurement based modeling methodology is proposed for characterization of coupled interconnects on silicon substrate. First, a set of single transmission lines in ground-signal-ground configuration is measured and modeled as multiple Gamma-sections. A pair of coupled lines is then modeled as two single lines interconnected by coupling capacitance, mutual inductance and mutual resistance. Asymptotic techniques and closed-form analytical expressions are used to determine the initial guesses for optimization of the model parameters of single and coupled lines. It is found that in extending the single line model to the coupled lines, only a couple of model parameters need to change due to the proximity effect. Further, the time-domain crosstalk is measured for Cu/oxide and Cu/Ultra low-kappa interconnects and analyzed using the proposed model. Good agreement is found between the simulated and measured results in both the frequency and the time domains for different lengths, widths and spacing (for coupled-lines) confirming the accuracy of the modeling methodology. The compact modeling approach presented here facilitates accurate characterization and modeling of coupled interconnects based on measured S-parameters data.

[1]  S. Krishnan,et al.  Loop-based inductance extraction and modeling for multiconductor on-chip interconnects , 2006, IEEE Transactions on Electron Devices.

[2]  Joungho Kim,et al.  An efficient crosstalk parameter extraction method for high-speed interconnection lines , 2000, ECTC 2000.

[3]  Hai Lan,et al.  Accurate closed-form expressions for the frequency-dependent line parameters of on-chip interconnects on lossy silicon substrate , 2001, IMS 2001.

[4]  David K. Walker,et al.  Asymmetric coupled CMOS lines-an experimental study , 2000 .

[5]  S.C. Rustagi,et al.  Wideband lumped element model for on-chip interconnects on lossy silicon substrate , 2006, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006.

[6]  T. Wong,et al.  Effects of Plasma Treatments on Ultralow-k Dielectric Film and Ta Barrier Properties in Cu Damascene Processing , 2006 .

[7]  Cheng-Nan Chiu Closed‐form expressions for the line‐coupling parameters of coupled on‐chip interconnects on lossy silicon substrate , 2004 .

[8]  A. Weisshaar,et al.  CAD-oriented equivalent-circuit modeling of on-chip interconnects on lossy silicon substrate , 2000 .

[9]  A. E. Ruehii Inductance Calculations in a Complex Integrated Circuit Environment , 2002 .

[10]  Franco Stellari,et al.  New formulas of interconnect capacitances based on results of conformal mapping method , 2000 .

[11]  David Blaauw,et al.  A simplified transmission-line based crosstalk noise model for on-chip RLC wiring , 2004 .