Characterization and modeling of CMOS on-chip coupled interconnects
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[1] S. Krishnan,et al. Loop-based inductance extraction and modeling for multiconductor on-chip interconnects , 2006, IEEE Transactions on Electron Devices.
[2] Joungho Kim,et al. An efficient crosstalk parameter extraction method for high-speed interconnection lines , 2000, ECTC 2000.
[3] Hai Lan,et al. Accurate closed-form expressions for the frequency-dependent line parameters of on-chip interconnects on lossy silicon substrate , 2001, IMS 2001.
[4] David K. Walker,et al. Asymmetric coupled CMOS lines-an experimental study , 2000 .
[5] S.C. Rustagi,et al. Wideband lumped element model for on-chip interconnects on lossy silicon substrate , 2006, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006.
[6] T. Wong,et al. Effects of Plasma Treatments on Ultralow-k Dielectric Film and Ta Barrier Properties in Cu Damascene Processing , 2006 .
[7] Cheng-Nan Chiu. Closed‐form expressions for the line‐coupling parameters of coupled on‐chip interconnects on lossy silicon substrate , 2004 .
[8] A. Weisshaar,et al. CAD-oriented equivalent-circuit modeling of on-chip interconnects on lossy silicon substrate , 2000 .
[9] A. E. Ruehii. Inductance Calculations in a Complex Integrated Circuit Environment , 2002 .
[10] Franco Stellari,et al. New formulas of interconnect capacitances based on results of conformal mapping method , 2000 .
[11] David Blaauw,et al. A simplified transmission-line based crosstalk noise model for on-chip RLC wiring , 2004 .