Methods and apparatus for decoding LDPC

A method of making the decoding processing message passing parity check using vectorized graphics LDPC representing high matrices parity check, therefore, a high control matrix parity element 0 of a matrix H parity check code LDPC projected are replaced by matrices of zeroes size zxz, and the elements 1 of the check matrix H parity are replaced by permutation matrices of size zxz, the method comprising the steps of: maintain L sets of messages K bits in a device (1506, 1607, 1707) for storing messages, each message set K bit first Z posts pass, where L and Z are positive greater than one integers and K is a positive integer other than zero, whereby each of said sets of Z K-bit messages or read is written as a single unit, using NDO one SIMD instruction; issuing read one of said sets of Z K-bit messages, from the device (1506, 1607, 1707) for storing messages; perform a reordering of messages on said set of Z messages read K bits to produce a reordered set of Z K-bit messages; supplying, in parallel, the Z messages in the set K bits reordered messages to a vector processor (1508, 1608, 1707) of nodes, including Z parallel processing units node; operate the vector processor (1508, 1608, 1707) of nodes to perform processing operations variable nodes, using as input the Z messages K bits supplied, by which a processing operation of variable nodes is performed in each of the Z units parallel processing nodes and a processing operation variable node includes generating a decision value, and examine the decision values ​​generated to determine whether a condition has been satisfied decoding.