Modeling of a pair of annular through silicon vias (TSV)

Modelling of a pair of annular TSVs is performed in this paper. A set of equivalent lumped-element circuit models for two annular TSV interconnects is proposed, with MOS capacitance effects treated appropriately. The method for characterizing its frequency- and temperature-dependent RLCG parameters is proposed, including its effective capacitance and conductance. The characteristic impedance and insertion loss are studied numerically.

[1]  Makoto Motoyoshi,et al.  Through-Silicon Via (TSV) , 2009, Proceedings of the IEEE.

[2]  F. Ulaby.  Fundamentals of applied electromagnetics , 1998 .

[3]  Jun-Fa Mao,et al.  A Study of On-Chip Stacked Multiloop Spiral Inductors , 2008, IEEE Transactions on Electron Devices.

[4]  B. Xie,et al.  Novel sequential electro-chemical and thermo-mechanical simulation methodology for annular through-silicon-via (TSV) design , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[5]  Eby G. Friedman,et al.  Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits , 2009, Proceedings of the IEEE.

[6]  Rao Tummala,et al.  Electrical modeling of annular and co-axial TSVs considering MOS capacitance effects , 2009, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems.

[7]  Mitsumasa Koyanagi,et al.  High-Density Through Silicon Vias for 3-D LSIs , 2009, Proceedings of the IEEE.