3.1–10.6 GHz UWB low-power CMOS power amplifier

This article presents a low-power consumption power amplifier that uses the TSMC 0.18-μm CMOS fabrication process and operates in the 3.1–10.6 GHz ultra-wideband (UWB). Additionally, the proposed circuit design uses only two stages for amplification. The proposed amplifier also improves gain flatness by using cascode topology and the current-reused technology to optimise the RC coupling between the two stages. The average gain is 13.1 ± 1 dB, input return loss (S11) is less than –5.5 dB and output return loss (S22) is less than –7 dB. Moreover, the output 1 dB compression point is about –1.5 dBm and output third-order cut-off point at 6 GHz is 12 dBm. The power consumption with 1.8-V supply voltage is 21 mW, and the chip area is 1.05 × 0.76 mm2.

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