Sectored caches have been used for many years in order to reconcile low tag array size and small or medium block size. In a sectored cache, a single address tag is associated with a sector consisting on several cache lines, while validity, dirty and coherency tags are associated with each of the inner cache lines. Usually in a cache, a cache line location is statically linked to one and only one address tag word location. In the decoupled sectored cache introduced in the paper, this monolithic association is broken; the address tag location associated with a cache line location is dynamically chosen at fetch time among several possible locations. The tag volume on a decoupled sectored cache is in the same range as the tag volume in a traditional sectored cache; but the hit ratio on a decoupled sectored cache is very close to the hit ratio on a non-sectored cache. A decoupled sectored cache will allow the same level of performance as a non-sectored cache, but at a significantly lower hardware cost.<<ETX>>
[1]
Alan Jay Smith,et al.
Line (Block) Size Choice for CPU Cache Memories
,
1987,
IEEE Transactions on Computers.
[2]
Alan Jay Smith,et al.
Evaluating Associativity in CPU Caches
,
1989,
IEEE Trans. Computers.
[3]
Alan Jay Smith,et al.
Second bibliography on Cache memories
,
1991,
CARN.
[4]
Edward S. Davidson,et al.
KSR1 multiprocessor: analysis of latency hiding techniques in a sparse solver
,
1993,
[1993] Proceedings Seventh International Parallel Processing Symposium.
[5]
Alan Jay Smith,et al.
Bibliography and reading on CPU cache memories and related topics
,
1986,
CARN.
[6]
James R. Goodman.
Using cache memory to reduce processor-memory traffic
,
1998,
ISCA '98.
[7]
Mark D. Hill,et al.
A case for direct-mapped caches
,
1988,
Computer.