Criticality computation in parameterized statistical timing

Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult since different paths are frequency-limiting in different parts of the multi-dimensional process space. Therefore, it is desirable to have a new diagnostic metric for robust circuit optimization. This paper presents a novel algorithm to compute the criticality probability of every edge in the timing graph of a design with linear complexity in the circuit size. Using industrial benchmarks, we verify the correctness of our criticality computation via Monte Carlo simulation. We also show that for large industrial designs with 442,000 gates, our algorithm computes all edge criticalities in less than 160 seconds

[1]  Chandu Visweswariah,et al.  Death, taxes and failing chips , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[2]  N.R. Malik,et al.  Graph theory with applications to engineering and computer science , 1975, Proceedings of the IEEE.

[3]  Vladimir Zolotov,et al.  Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[4]  K. Ravindran,et al.  First-Order Incremental Block-Based Statistical Timing Analysis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Narsingh Deo,et al.  Graph Theory with Applications to Engineering and Computer Science , 1975, Networks.

[6]  Vladimir Zolotov,et al.  Gate sizing using incremental parameterized statistical timing analysis , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[7]  Sachin S. Sapatnekar,et al.  Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal , 2003, ICCAD 2003.

[8]  C. E. Clark The Greatest of a Finite Set of Random Variables , 1961 .

[9]  David Blaauw,et al.  Circuit optimization using statistical static timing analysis , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[10]  Lawrence T. Pileggi,et al.  Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[11]  David Blaauw,et al.  Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[12]  Bajis M. Dodin,et al.  Approximating the Criticality Indices of the Activities in PERT Networks , 1985 .