VLSI Circuit Performance Optimization by Geometric Programming

Delay of VLSI circuit components can be controlled by varying their sizes. In other words, performance of VLSI circuits can be optimized by changing the sizes of the circuit components. In this paper, we define a special type of geometric program called unary geometric program. We show that under the Elmore delay model, several commonly used formulations of the circuit component sizing problem considering delay, chip area and power dissipation can be reduced to unary geometric programs. We present a greedy algorithm to solve unary geometric programs optimally and efficiently. When applied to VLSI circuit component sizing, we prove that the runtime of the greedy algorithm is linear to the number of components in the circuit. In practice, we demonstrate that our unary-geometric-program based approach for circuit sizing is hundreds of times or more faster than other approaches.

[1]  Lawrence T. Pileggi,et al.  RC interconnect synthesis-a moment fitting approach , 1994, ICCAD.

[2]  Jason Cong,et al.  Optimal wiresizing under Elmore delay model , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  David Marple.  Transistor Size Optimization in the Tailor Layout System , 1989, 26th ACM/IEEE Design Automation Conference.

[4]  Martin D. F. Wong,et al.  Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[5]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[6]  Clarence Zener,et al.  Geometric Programming : Theory and Application , 1967 .

[7]  Lawrence T. Pileggi,et al.  Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization , 1995, 32nd Design Automation Conference.

[8]  Hai Zhou,et al.  Optimal non-uniform wire-sizing under the Elmore delay model , 1996, Proceedings of International Conference on Computer Aided Design.

[9]  Jason Cong,et al.  Optimal wiresizing under the distributed Elmore delay model , 1993, ICCAD '93.

[10]  Jason Cong,et al.  An efficient approach to simultaneous transistor and interconnect sizing , 1996, Proceedings of International Conference on Computer Aided Design.

[11]  Sachin S. Sapatnekar,et al.  RC Interconnect Optimization under the Elmore Delay Model , 1994, 31st Design Automation Conference.

[12]  Sung-Mo Kang,et al.  An exact solution to the transistor sizing problem for CMOS circuits using convex optimization , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Martin D. F. Wong,et al.  Greedy wire-sizing is linear time , 1998, ISPD '98.

[14]  Mehmet A. Cirit.  Transistor Sizing in CMOS Circuits , 1987, 24th ACM/IEEE Design Automation Conference.

[15]  M. Morris Mano,et al.  Digital Logic and Computer Design , 1979 .

[16]  John P. Fishburn,et al.  TILOS: A posynomial programming approach to transistor sizing , 2003, ICCAD 2003.

[17]  Yao-Wen Chang,et al.  Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation , 1996, 33rd Design Automation Conference Proceedings, 1996.

[18]  Ross Baldick,et al.  A sequential quadratic programming approach to concurrent gate and wire sizing , 1995, ICCAD.

[19]  Lawrence T. Pillage,et al.  Rc Interconnect Synthesis-a Moment Fitting Approach , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[20]  Alberto Sangiovanni-Vincentelli,et al.  Optimization-based transistor sizing , 1988 .

[21]  Jason Cong,et al.  Simultaneous driver and wire sizing for performance and power optimization , 1994, ICCAD.