A performance driven generator for efficient testable conditional-sum-adders

The authors present a performance driven generator for integer adders which is parameterized in n, the operands' bit length, t/sub n/, the delay of the addition, and FM, the (cell based static) fault model. FM may in particular be chosen as the classical stuck-at fault model or the cellular fault model. The output of the generator is an area-minimal n-bit adder of the conditional-sum type with delay <or=t/sub n/ (if such a circuit exists at all). The number of test vectors constructed is bounded by O(n/sup 2/). The running time of the generator itself is about c*n/sup 2/*t/sub n/ where c is a small constant.<<ETX>>