Low-Power and Low-Voltage Communication for SOC´s

[1]  Majid Sarrafzadeh,et al.  Simultaneous scheduling, binding and floorplanning for interconnect power optimization , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[2]  T. Haulin,et al.  I/O family with 200 mV to 500 mV supply voltage , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[3]  Christer Svensson,et al.  Low-power, low-latency global interconnect , 2002, 15th Annual IEEE International ASIC/SOC Conference.

[4]  Atila Alvandpour,et al.  GLMC: interconnect length estimation by growth-limited multifold clustering , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[5]  Taiichi Otsuji,et al.  Analysis and application of a novel model for estimating power dissipation of optical interconnections as a function of transmission bit error rate , 1996 .

[6]  Stefan Hirsch,et al.  CMOS receiver circuits for high-speed data transmission according to LVDS-standard , 2003, SPIE Microtechnologies.

[7]  Mircea R. Stan,et al.  Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[8]  D. Miller Optics for low-energy communication inside digital processors: quantum detectors, sources, and modulators as efficient impedance converters. , 1989, Optics letters.

[9]  Christer Svensson,et al.  A comparison of dissipated power and signal-to-noise ratios in electrical and optical interconnects , 1999 .

[10]  William C. Athas,et al.  A sub-CV/sup 2/ pad driver with 10 ns transition time , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[11]  Hiroaki Misawa,et al.  Data-dependent logic swing internal bus architecture for ultralow-power lsi's. ieee j. solid-state , 1995 .

[12]  Dake Liu,et al.  Power consumption estimation in CMOS VLSI chips , 1994, IEEE J. Solid State Circuits.

[13]  Anantha P. Chandrakasan,et al.  Low power bus coding techniques considering inter-wire capacitances , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[14]  C. Svensson Optimum voltage swing on on-chip and off-chip interconnects , 2000, Proceedings of the 26th European Solid-State Circuits Conference.

[15]  Christer Svensson Electrical interconnects revitalized , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Yasuhiko Sasaki,et al.  Crosstalk delay analysis of a 0.13-/spl mu/m node test chip and precise gate-level simulation technology , 2003 .

[17]  Christer Svensson,et al.  High-bandwidth low-latency global interconnect , 2003, SPIE Microtechnologies.

[18]  Massoud Pedram,et al.  BEAM: bus encoding based on instruction-set-aware memories , 2003, ASP-DAC '03.

[19]  Pawan Kapur,et al.  Power estimation in global interconnects and its reduction using a novel repeater optimization methodology , 2002, DAC '02.

[20]  Ram Krishnamurthy,et al.  A transition-encoded dynamic bus technique for high-performance interconnects , 2003 .

[21]  William J. Dally,et al.  Digital systems engineering , 1998 .

[22]  Krishna C. Saraswat,et al.  Scaling trends for the on chip power dissipation , 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).

[23]  Hiroyuki Yamauchi,et al.  An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI's(Special Issue on the 1994 VLSI Circuits Symposium) , 1995 .

[24]  Massoud Pedram,et al.  Architectural energy optimization by bus splitting , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Massoud Pedram,et al.  High-level power modeling, estimation, and optimization , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  Nestoras Tzartzanis,et al.  Low-power digital systems based on adiabatic-switching principles , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[27]  Krishnamurthy Soumyanath,et al.  Accurate on-chip interconnect evaluation: a time-domain technique , 1999 .