Modelování a Implementace SubsystéMů KomunikačníHo řetěZce V Obvodech FPGA ; Communication Chain sub-Block modelling and Implementation in FPGA

Most modern clock and data recovery circuits (CDR) are based on analog blocks that need to be redesigned whenever the technology process is to be changed. On the other hand, CDR based blind oversampling architecture (BO-CDR) can be completely designed in a digital process which makes its migration very simple. The main disadvantages of the BO-CDR that are usually mentioned in a literature are complexity of its digital circuitry and finite phase resolution resulting in larger jitter sensitivity and higher error rate. This thesis will show that those problems can be solved by designing a new algorithm of BO-CDR and subsequent optimization. For this task an FPGA was selected as simulation and verification platform. This enables to change parameters of the optimized circuit in real time while measuring on real links (unlike a simulation using inaccurate link models). The output of this optimization is a new BO-CDR algorithm with heavily reduced complexity and very low error rate. A new FPGA-based method of jitter measurement was developed (primary for CDR analysis), which enables a quick link characterization without using probing or additional equipment. The new method requires only a minimum usage of FPGA resources. Finally, new measurement equipment was developed to measure bit error distribution on FSO links to be able to develop a suitable error correction scheme based on ARQ protocol.

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