A nonvolatile analog neural memory using floating-gate MOS transistors

Simple floating-gate transistors fabricated by a conventional double-polysilicon process show excellent programming and charge-retention characteristics. A five-transistor synapse cell achieves 8-bit resolution and at least 6-bit accuracy for analog neural computation. It occupies 67 μm×73 μm in a 2-μm CMOS process and can retain charge accuracy for over 25 years.

[1]  C. Tomovich,et al.  MOSIS - A gateway to silicon , 1988, IEEE Circuits and Devices Magazine.

[2]  Katsuyuki Kaneko,et al.  A 64 b RISC microprocessor for a parallel computer system , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[3]  L. Carley,et al.  Trimming analog circuits using floating-gate analog MOS memory , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[4]  Jin Luo,et al.  CMOS UV-writable non-volatile analog storage , 1991 .

[5]  L. Kohn,et al.  A 1,000,000 transistor microprocessor , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[6]  H.P. Graf,et al.  A reconfigurable CMOS neural network , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[7]  S. Tam,et al.  An electrically trainable artificial neural network (ETANN) with 10240 'floating gate' synapses , 1990, International 1989 Joint Conference on Neural Networks.

[8]  S. Bibyk,et al.  A neural network integrated circuit utilizing programmable threshold voltage devices , 1989, IEEE International Symposium on Circuits and Systems,.

[9]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .