Impact of TSV and Device Scaling on the Quality of 3D ICs

TSVs have negative effects such as area, delay, and power overhead because of non-negligible TSV area and capacitance. Therefore, obtaining benefits such as wirelength reduction and performance improvement from 3D integration is highly dependent on the TSV size and capacitance. To reduce the negative effects, TSVs have been downscaled and sub-micron TSVs are expected to be commercially available in the near future. Meanwhile, devices have also been downscaled beyond 32 and 22 nm, so future 3D ICs will very likely be built with sub-micron TSVs and advanced device technologies. In this chapter, the impact of TSVs on the quality of today and future 3D ICs is investigated based on GDSII-level layouts.

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