Feedback driven high level synthesis for performance optimization

We propose a high level synthesis design flow in order to improve the circuit performance once the placement phase is done. We use a high level synthesis system known as automatic design instantiation (AUDI) to generate a register-transfer level (RTL) netlist. This netlist is then given to a Xilinx CAD tool for physical synthesis. Instead of routing the design right after the placement phase, we make use of the estimated interconnect delay, generate a guidance and give it to the high level synthesis system. The guidance consists of estimated timing information as well as instructions for producing a new netlist to improve the circuit performance. The design is finally routed on a satisfying design. This performance-driven high level synthesis framework yields significantly better results as compared with designs generated by a plain top-down design flow

[1]  Donald E. Thomas,et al.  The combination of scheduling, allocation, and mapping in a single algorithm , 1991, DAC '90.

[2]  Forrest Brewer,et al.  Automata-Based Symbolic Scheduling for Looping DFGs , 2001, IEEE Trans. Computers.

[3]  Daniel P. Siewiorek,et al.  Facet: A Procedure for the Automated Synthesis of Digital Systems , 1983, 20th Design Automation Conference Proceedings.

[4]  Srinivas Katkoori,et al.  Knapbind: an area-efficient binding algorithm for low-leakage datapaths , 2003, Proceedings 21st International Conference on Computer Design.

[5]  R. Composano,et al.  Path-based scheduling for synthesis , 1990, Twenty-Third Annual Hawaii International Conference on System Sciences.

[6]  Srinivas Katkoori,et al.  Tabu search based behavioural synthesis of low leakage datapaths , 2004, IEEE Computer Society Annual Symposium on VLSI.

[7]  Kiyoung Choi,et al.  Behavior-to-placed RTL synthesis with performance-driven placement , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[8]  P.G. Paulin,et al.  Algorithms for high-level synthesis , 1989, IEEE Design & Test of Computers.

[9]  Fadi J. Kurdahi,et al.  Layout-driven high level synthesis for FPGA based architectures , 1998, Proceedings Design, Automation and Test in Europe.

[10]  Deming Chen,et al.  Low-power high-level synthesis for FPGA architectures , 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

[11]  J. Cortadella,et al.  Scheduling and resource binding for low power , 1995 .

[12]  Fadi J. Kurdahi,et al.  Layout-driven RTL binding techniques for high-level synthesis , 1996, Proceedings of 9th International Symposium on Systems Synthesis.