A comparison of FFT processor designs

ASTRON is the Netherlands Institute for Radio Astronomy. They operate, among others, LOFAR (Low Frequency Array), which is a radio telescope using a concept based on a large array of omni-directional antennas. The signals from these antennas go through various processing units, one of which is an FFT processor. In the current LOFAR design, FPGAs are used for this, since the numbers are too small to a�ord custom chips. For future astronomical applications, especially for the SKA telescope, a more speci�c chip solution is desired. SKA will be much larger than LOFAR and use many more processing elements. As power consumption is a major concern, the FPGAs are unsuitable and they need to be replaced with ASICs. The energy consumption of the FPGAs is compared to the energy comsumption of the same FFT design implemented on an ASIC. For the FPGA synthesis and power calculation, Quartus is used. The ASIC was synthesized with Synopsys Design Compiler using 65nm technology. The energy usage is reduced from 0.84�J per FFT on the FPGA to 0.41�J per FFT on the ASIC. Four new ASIC designs are compared to the existing one, in search of a better solution. An approach that uses the minimal amount of memory (SDF), and one that uses more memory for faster calculation (MDC) are implemented for both radix-2 and radix-4 designs. Di�erent complex multipliers and di�erent methods of storing the twiddle factors are also compared. The fast calculating radix-2 design gives the best results. Combined with a complex multiplier that uses Gauss' complex multiplication algorithm and a twiddle factor component based on registers, the energy comsumption per FFT can be reduced to 0.33�J.