Digital-intensive RFIC design techniques for transmitters in ISSCC 2023

Sub-6 GHz multi-standard wireless communication and millimeter-wave (mm-wave) wireless transmission provide users with multi-functionality and unprecedented wireless connectivity. With CMOS process scaling down, system-on-chip (SoC) implementation of wireless systems along with RFIC functionality is highly desirable for low cost and small form-factor. The digital transceiver architecture aligns with Moore’s law to provide compact die area, better interface to digital backend and higher efficiency due to the faster switching nature of core devices[1−28]. The digital PA (DPA) plays a dominant role in digital transmitters (DTXs), which performs digital-to-analog conversion, frequency up-conversion and power amplification all-in-one. Since modern wireless standards widely adopt orthogonal frequency division multiplexing (OFDM) and high-order quadrature amplitude modulation (QAM) to increase throughput and spectral utilization, it requires the DPA to achieve high output power (e.g., >30 dBm), high linearity and high efficiency especially at back-off power levels. Relevant intensive researches at sub-6 GHz have been directed toward class-D based switched-capacitor PAs, which are more amenable to CMOS scaling and have good linearity and efficiency due to fast low-loss switches and precise capacitor matching. In ISSCC 2023, two works on sub-6 GHz DTX/DPA came from Fudan University[5, 7]. In Ref. [5], a singlechannel quadrature DTX supporting multi-mode multi-band NB-IoT/BLE applications is proposed. It introduces a sliding digital-IF quadrature architecture to replace the fractional upsampling module and achieve pure output spectrum. Besides, a compact wideband Doherty DPA with IQ cell-sharing is implemented to enhance output power and back-off efficiency. This multi-mode NB-IoT/BLE DTX chip achieves Watt-level peak power with >40% system efficiency while occupying only 0.79 mm2 core area, which is well-fitting lowcost IoT applications. In Ref. [7], a 4.1 W quadrature DPA with 33.6% peak PAE in 28 nm bulk CMOS is presented. It introduces the cascode and 8-way differential power-combining techniques to enhance output power by 16 times. Besides, the IQ cell-sharing and transformer-based Doherty techniques are introduced to further enhance output power by 2 times and achieve 12 efficiency peaks in the complex domain. Powered by 1.1 V/2.2 V supply voltages and packaged in an QFN format, this DPA chip achieves 4.1 W peak power and close-to-Watt-level average power with competitive efficiency performance even compared with polar DPAs, which is very attractive for compact and fast system integration in 5G applications. mm-wave wireless transmission with multi-Gb/s data rate also demands wideband signal processing, high system efficiency and high output power for large coverage. In ISSCC 2023, a 71–89 GHz DPA came from University of Electronic Science and Technology of China[26]. In Ref. [26], the doubleedge-triggered technique is proposed to double the signal bandwidth with limited sampling clock. Besides, the LO leakage suppression and balance-compensated power-combining techniques are introduced to enhance linearity and efficiency. Implemented in 40 nm CMOS, this mm-wave DPA obtains 12 Gb/s high-speed data rate, 20.5 dBm peak output power and 20.4% system efficiency, which is quite competitive for E-band wireless applications. Moreover, two DTX works are implemented for FMCW chirps from Infineon Technologies[27] and low-power cryogenic controller IC design from Tsinghua University[28]. In Ref. [27], accurate frequency modulation of a direct digital frequency synthesizer is combined with the RFDAC to generate precise wide-bandwidth frequency ramps, which achieves 4 GHz modulation bandwidth with <3 dB power variation. In Ref. [28], a polar architecture with DPA-based amplitude modulation and injection-locking LO based phase modulation is proposed. Its power consumption is 13.7 mW per qubit under active control and the average chip area per channel is only 0.9 mm2. In Table 1, various DTX/DPAs operating from sub-6 GHz to mm-wave bands with multi-mode multi-band, output power, good efficiency, linearity and bandwidth have been summarized. With these advanced metrics, the digital RF front-end will be a good candidate for modern and further wireless applications.

[1]  H. Qian,et al.  71-to-89GHz 12Gb/s Double-Edge-Triggered Quadrature RFDAC with LO Leakage Suppression Achieving 20.5dBm Peak Output Power and 20.4% System Efficiency , 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

[2]  Hongtao Xu,et al.  A 4.1 W Quadrature Doherty Digital Power Amplifier with 33.6% Peak PAE in 28nm Bulk CMOS , 2023, IEEE International Solid-State Circuits Conference.

[3]  Ning Deng,et al.  A Polar-Modulation-Based Cryogenic Qubit State Controller in 28nm Bulk CMOS , 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

[4]  Wei Li,et al.  31.7 A 0.7-to-2.5GHz Sliding Digital-IF Quadrature Digital Transmitter Achieving >40% System Efficiency for Multi-Mode NB-IoT/BLE Applications , 2023, IEEE International Solid-State Circuits Conference.

[5]  H. Qian,et al.  A CMOS Wideband Watt-Level 4096-QAM Digital Power Amplifier Using Reconfigurable Power-Combining Transformer , 2023, IEEE Journal of Solid-State Circuits.

[6]  Hongtao Xu,et al.  A Fully-Integrated Wideband Digital Polar Transmitter With 11-bit Digital-to-Phase Converter in 40nm CMOS , 2023, IEEE Journal of Solid-State Circuits.

[7]  Zhao Zhang,et al.  Trending IC design directions in 2022 , 2022, Journal of Semiconductors.

[8]  J. Walling,et al.  A mm-Wave Switched-Capacitor RFDAC , 2022, IEEE Journal of Solid-State Circuits.

[9]  Assaf Ben Bassat,et al.  A 16nm, +28dBm Dual-Band All-Digital Polar Transmitter Based on 4-core Digital PA for Wi-Fi6E Applications , 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

[10]  Xun Luo,et al.  Quadrature Switched/Floated Capacitor Power Amplifier With Reconfigurable Self-Coupling Canceling Transformer for Deep Back-Off Efficiency Enhancement , 2021, IEEE Journal of Solid-State Circuits.

[11]  Shih-Chang Hung,et al.  A Quadrature Class-G Complex-Domain Doherty Digital Power Amplifier , 2021, IEEE Journal of Solid-State Circuits.

[12]  Hongtao Xu,et al.  A Quadrature Digital Power Amplifier With Hybrid Doherty and Impedance Boosting for Complex Domain Power Back-Off Efficiency Enhancement , 2021, IEEE Journal of Solid-State Circuits.

[13]  Hao Min,et al.  A Broadband Switched-Transformer Digital Power Amplifier for Deep Back-Off Efficiency Enhancement , 2020, IEEE Journal of Solid-State Circuits.

[14]  Yorgos Palaskas,et al.  A Cellular Multiband DTC-Based Digital Polar Transmitter With −153-dBc/Hz Noise in 14-nm FinFET , 2020, IEEE Journal of Solid-State Circuits.

[15]  Behzad Razavi,et al.  A Digital RF Transmitter With Background Nonlinearity Correction , 2020, IEEE Journal of Solid-State Circuits.

[16]  Sensen Li,et al.  A CMOS 1.2-V Hybrid Current- and Voltage-Mode Three-Way Digital Doherty PA With Built-In Phase Nonlinearity Compensation , 2020, IEEE Journal of Solid-State Circuits.

[17]  Liang Xiong,et al.  24.5 A 15b Quadrature Digital Power Amplifier with Transformer-Based Complex-Domain Power-Efficiency Enhancement , 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

[18]  Jeffrey S. Walling,et al.  10.7 A 0.26mm2 DPD-Less Quadrature Digital Transmitter With <−40dB EVM Over >30dB Pout Range in 65nm CMOS , 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

[19]  Shih-Chang Hung,et al.  24.4 A Watt-Level Multimode Multi-Efficiency-Peak Digital Polar Power Amplifier with Linear Single-Supply Class-G Technique , 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

[20]  Xun Luo,et al.  A 20–32-GHz Quadrature Digital Transmitter Using Synthesized Impedance Variation Compensation , 2020, IEEE Journal of Solid-State Circuits.

[21]  R. Banin,et al.  A Cellular Multiband DTC-Based Digital Polar Transmitter With −153 dBc/Hz Noise in 14-nm FinFET , 2019, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC).

[22]  Mikko Valkama,et al.  A 1.5–1.9-GHz All-Digital Tri-Phasing Transmitter With an Integrated Multilevel Class-D Power Amplifier Achieving 100-MHz RF Bandwidth , 2019, IEEE Journal of Solid-State Circuits.

[23]  Sang-Min Yoo,et al.  A Quadrature Class-G Complex-Domain Doherty Digital Power Amplifier , 2019, 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

[24]  Elbert Bechthum,et al.  A CMOS Polar Class-G Switched-Capacitor PA With a Single High-Current Supply, for LTE NB-IoT and eMTC , 2019, IEEE Journal of Solid-State Circuits.

[25]  Shih-Chang Hung,et al.  A Watt-Level Quadrature Class-G Switched-Capacitor Power Amplifier With Linearization Techniques , 2019, IEEE Journal of Solid-State Circuits.

[26]  Tong Li,et al.  A Compact Transformer-Combined Polar/Quadrature Reconfigurable Digital Power Amplifier in 28-nm Logic LP CMOS , 2019, IEEE Journal of Solid-State Circuits.

[27]  Mike Shuo-Wei Chen,et al.  A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement , 2019, IEEE Journal of Solid-State Circuits.

[28]  Hao Min,et al.  A Compact Dual-Band Digital Polar Doherty Power Amplifier Using Parallel-Combining Transformer , 2019, IEEE Journal of Solid-State Circuits.

[29]  Wen Yuan,et al.  4.3 A Multiphase Interpolating Digital Power Amplifier for TX Beamforming in 65nm CMOS , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).