On analysis of fabricated polymorphic circuits

The paper describes a reconfigurable polymorphic chip REPOMO32, experiments carried out with this chip and provides report on important experiences with regard to practical applications of digital polymorphic circuits sensitive to the power supply voltage (Vdd). REPOMO32 contains array of 32 configurable logic elements which can perform polymorphic NAND/NOR function controlled by the level of the Vdd. Moreover, it can be declared as the first fabricated chip of this kind which basically allows the user to design more complex circuits than only a few gates.

[1]  Adrian Stoica,et al.  Three-Function Logic Gate Controlled by Analog Voltage , 2006 .

[2]  Xin Guo,et al.  Taking evolutionary circuit design from experimentation to implementation: some useful techniques and a silicon demonstration , 2004 .

[3]  Lukás Sekanina,et al.  Physical Demonstration of Polymorphic Self-Checking Circuits , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[4]  Wenjian Luo,et al.  Designing polymorphic circuits with polymorphic gates: a general design approach , 2007, IET Circuits Devices Syst..

[5]  Lukás Sekanina,et al.  Polymorphic FIR Filters with Backup Mode Enabling Power Savings , 2009, 2009 NASA/ESA Conference on Adaptive Hardware and Systems.

[6]  Adrian Stoica,et al.  On Polymorphic Circuits and Their Design Using Evolutionary Algorithms , 2002 .

[7]  Lukás Fujcik,et al.  REPOMO32 - New reconfigurable polymorphic integrated circuit for adaptive hardware , 2009, 2009 IEEE Workshop on Evolvable and Adaptive Hardware.

[8]  Lukás Sekanina,et al.  Evolutionary Design of Gate-Level Polymorphic Digital Circuits , 2005, EvoWorkshops.

[9]  Lukás Sekanina,et al.  Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming , 2009, 2009 IEEE Congress on Evolutionary Computation.

[10]  Richard Ruzicka.  On bifunctional polymorphic gates controlled by a special signal , 2008 .

[11]  Adrian Stoica,et al.  Polymorphic Electronics , 2001, ICES.

[12]  Kyrre Glette,et al.  2009 NASA/ESA Conference on Adaptive Hardware and Systems , 2009 .

[13]  Zdenek Kotásek,et al.  Polymorphic Gates in Design and Test of Digital Circuits , 2008, Int. J. Unconv. Comput..

[14]  Zdenek Kotásek,et al.  Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration , 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.