An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems

This paper presents a multimode FFT processor for wireless personal area network (WPAN), wireless local area network (WLAN), and wireless metropolitan area network (WMAN) applications. Using the proposed flexible-radix-configuration multipath-delay-feedback (FRCMDF) architecture, variable-length/multiple-stream FFTs capable of achieving a high throughput can be performed in a hardware-efficient manner. Based on the FRCMDF structure, a dual-optimized multiplication scheme is also proposed to further improve the area and energy efficiency. In addition, the proposed configuration scheme can provide an architectural support for power scalability across FFT modes. A test chip for the proposed FFT processor has been designed and fabricated using a TSMC-0.18 m CMOS process with a core size of 3.2 mm^2 and a signal-to-quantization-noise ratio (SQNR) of over 40 dB. When the FFT mode is configured to operate as a 2.4 GS/s 512-point FFT at 300 MHz, the measured power consumption is 507 mW. Compared with previous multimode FFT designs, our FFT chip is more area- and energy-efficient as it is able to provide relatively higher throughput per unit area or per unit power consumption. Also, the power scalability across FFT modes is relatively exhibited in the proposed FFT processor.

[1]  Chen-Yi Lee,et al.  A 1-GS/s FFT/IFFT processor for UWB applications , 2005, IEEE J. Solid State Circuits.

[2]  Keshab K. Parhi,et al.  Low error fixed-width CSD multiplier with efficient sign extension , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[3]  Song-Nien Tang,et al.  A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[4]  Sau-Gee Chen,et al.  A green FFT processor with 2.5-GS/s for IEEE 802.15.3c (WPANs) , 2010, The 2010 International Conference on Green Circuits and Systems.

[5]  Pei-Yun Tsai,et al.  Low-power variable-length fast Fourier transform processor , 2005 .

[6]  Chen-Yi Lee,et al.  An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Manoj Sachdev,et al.  Variation-Aware Adaptive Voltage Scaling System , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Guoping Zhang,et al.  Parallel FFT with CORDIC for ultra wide band , 2004, 2004 IEEE 15th International Symposium on Personal, Indoor and Mobile Radio Communications (IEEE Cat. No.04TH8754).

[9]  Chao-Ming Chen,et al.  An Energy-Efficient Partial FFT Processor for the OFDMA Communication System , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  A.N. Willson,et al.  A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring , 2006, IEEE Journal of Solid-State Circuits.

[11]  An-Yeu Wu,et al.  Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Viktor Öwall,et al.  A 2048 complex point FFT processor using a novel data scaling approach , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[13]  Tsin-Yuan Chang,et al.  High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[15]  U. Jagdhold,et al.  A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM , 2004, IEEE Journal of Solid-State Circuits.

[16]  Swapna Banerjee,et al.  Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture , 2005, IEEE Transactions on Circuits and Systems for Video Technology.

[17]  René van Leuken,et al.  A multistandard FFT processor for wireless system-on-chip implementations , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[18]  Bevan M. Baas,et al.  A low-power, high-performance, 1024-point FFT processor , 1999, IEEE J. Solid State Circuits.

[19]  Yi-Hsien Lin,et al.  A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[20]  Alvin M. Despain,et al.  Fourier Transform Computers Using CORDIC Iterations , 1974, IEEE Transactions on Computers.

[21]  Shousheng He,et al.  Designing pipeline FFT processor for OFDM (de)modulation , 1998, 1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No.98EX167).

[22]  José Francisco López,et al.  A CORDIC processor for FFT computation and its implementation using gallium arsenide technology , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[23]  Keshab K. Parhi,et al.  Design of low-error fixed-width modified booth multiplier , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[24]  Tian-Sheuan Chang,et al.  Architecture Design of Shape-Adaptive Discrete Cosine Transform and Its Inverse for MPEG-4 Video Coding , 2008, IEEE Transactions on Circuits and Systems for Video Technology.

[25]  An-Yeu Wu,et al.  A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[26]  Chen-Yi Lee,et al.  A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems , 2008, IEEE Journal of Solid-State Circuits.

[27]  Yin-Tsung Hwang,et al.  Scalable FFT kernel designs for MIMO OFDM based communication systems , 2007, TENCON 2007 - 2007 IEEE Region 10 Conference.

[28]  Hanho Lee,et al.  A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[29]  Javier D. Bruguera,et al.  High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm , 1997, IEEE Trans. Computers.