Test-per-Clock Detection, Localization and Identification of Interconnect Faults

The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction. The above-mentioned operations are made at-speed. The testing process has been split into two steps. The first one is the detection step using a short test sequence of little diagnostic resolution. The second step is the localization step by means of a long, full diagnostic resolution sequence and it is made only in the case of the detection of faults in the first step. The final fault identification phase exploits information stored in the signatures. Because the signature is chosen to be 32 bit long aliasing is negligible. The proposed hardware concept is independent of the type of both the detection test sequence and the localization test sequence. The theory given in the paper is illustrated by the simulation results. Moreover the paper proposes to test testing hardware itself what makes the results reliable

[1]  Tomasz Garbolino,et al.  On detection of interconnect faults by a MISR compactor-unknown problems and new solutions , 2005 .

[2]  Chauchin Su,et al.  Boundary scan BIST methodology for reconfigurable systems , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[3]  Abhijit Chatterjee,et al.  Switching activity generation with automated BIST synthesis forperformance testing of interconnects , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Benoit Nadeau-Dostie,et al.  An embedded technique for at-speed interconnect testing , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[5]  Tomasz Garbolino,et al.  Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path , 2000, Proceedings IEEE European Test Workshop.

[6]  Yervant Zorian,et al.  Towards a standard for embedded core test: an example , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[7]  Chauchin Su,et al.  Configuration free SoC interconnect BIST methodology , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[8]  Vinod K. Agarwal,et al.  Testing and diagnosis of interconnects using boundary scan architecture , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[9]  Artur Jutman,et al.  At-speed on-chip diagnosis of board-level interconnect faults , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[10]  Sungju Park,et al.  A new IEEE 1149.1 boundary scan design for the detection of delay defects , 2000, DATE '00.

[11]  Paul Wagner,et al.  INTERCONNECT TESTING WITH BOUNDARY SCAN , 1987 .

[12]  A. Hlawiczka,et al.  Dependable testing of compactor MISR: an imperceptible problem? , 2002, Proceedings The Seventh IEEE European Test Workshop.