Test response compaction using multiplexed parity trees

Built-in self-testing requires test response streams from many observation points to be merged (space compaction) and compressed (time compaction) into a short signature. The compaction circuits should be transparent to error propagation in order to minimize aliasing, which occurs when a faulty response maps to the fault-free signature. We investigate the use of multiplexed parity trees (MPTs) for zero-aliasing space compaction. MPTs combine the error propagation properties of multiplexers and parity trees, and ensure zero aliasing via multistep compaction. We present two design techniques based on MPTs-output selection and fanout insertion-that eliminate aliasing for both deterministic and pseudorandom test sets. Our experiments with the ISCAS benchmark circuits show that zero aliasing can be achieved with small test sets and moderate hardware overhead. We also demonstrate that a very high percentage of single stuck-line faults in the compaction circuit are detected by the test patterns applied to the circuit under test.

[1]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[2]  Irith Pomeranz,et al.  On achieving zero aliasing for modeled faults , 1992, [1992] Proceedings The European Conference on Design Automation.

[3]  Akihiro Yamamoto,et al.  Parity-Scan Design to Reduce the Cost of Test Application , 1992, Proceedings International Test Conference 1992.

[4]  Brian T. Murray.  Hierarchical testing using precomputed tests for modules , 1995 .

[5]  Daniel Brand.  Verification of large synthesized designs , 1993, ICCAD.

[6]  Dong Sam Ha,et al.  AN EFFICIENT, FORWARD FAULT SIMULATION ALGORITHM BASED ON THE PARALLEL PATTERN SINGLE FAULT PROPAGAT , 1991, 1991, Proceedings. International Test Conference.

[7]  Donald H. Lenhert,et al.  An ALU-based programmable MISR/pseudorandom generator for a MC68HC11 family self-test , 1993, Proceedings of IEEE International Test Conference - (ITC).

[8]  Yervant Zorian,et al.  Selecting programmable space compactors for BIST using genetic algorithms , 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

[9]  John P. Hayes.  On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests , 1971, IEEE Transactions on Computers.

[10]  Wen-Ben Jone,et al.  Multiple Fault Detection in Parity Checkers , 1993, IEEE Trans. Computers.

[11]  J. P. Robinson,et al.  Space Compression Methods With Output Data Modification , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  John P. Hayes,et al.  Efficient test response compression for multiple-output circuits , 1994, Proceedings., International Test Conference.

[13]  John P. Hayes,et al.  Implementation of VLSI self-testing by regularization , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Yervant Zorian,et al.  Programmable space compaction for BIST , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

[15]  John P. Hayes,et al.  High-level test generation using physically-induced faults , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[16]  Sudhakar M. Reddy,et al.  A Data Compression Technique for Built-In Self-Test , 1988, IEEE Trans. Computers.

[17]  William H. Kautz.  Testing for Faults in Combinational Cellular Logic Arrays , 1967, SWAT.

[18]  Irith Pomeranz,et al.  COMPACTEST: a method to generate compact test sets for combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..