A 4.6W/mm2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS

The future trends in microprocessor supply current requirements represent a bottleneck for next generation high-performance microprocessors since the number of supply pins will constitute an increasingly larger fraction of the total number of package pins available. This leaves few pins available for signaling. On-chip power conversion is a means to overcome this limitation by increasing the input voltage - thereby reducing the input current - and performing the final power conversion on the chip itself. This paper details the design and implementation of on-chip switched capacitor converters in deep submicron technologies. High capacitance density deep trench capacitors with a low parasitic bottom plate capacitor ratio available in the technology facilitate high power density and efficiency in on-chip switched capacitor converter implementations. The measured performance of a 2 : 1 voltage conversion ratio on-chip switched capacitor converter implemented in 32nm SOI CMOS technology with 1.8V input voltage results in a power density of 4.6W/mm2 at 86% efficiency when operated at a switching frequency of 100MHz.

[1]  Anantha P. Chandrakasan,et al.  A 0.16mm2 completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[2]  R. Dennard,et al.  A fully-integrated switched-capacitor 2∶1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm2 , 2010, 2010 Symposium on VLSI Circuits.

[3]  Michael Douglas Seeman,et al.  A Design Methodology for Switched-Capacitor DC-DC Converters , 2009 .

[4]  Thomas Brunschwiler,et al.  Experimental Investigation of an Ultrathin Manifold Microchannel Heat Sink for Liquid-Cooled Chips , 2010 .

[5]  M. Steyaert,et al.  A 1.65W fully integrated 90nm Bulk CMOS Intrinsic Charge Recycling capacitive DC-DC converter: Design & techniques for high power density , 2011, 2011 IEEE Energy Conversion Congress and Exposition.

[6]  Sigmond Singer,et al.  Capacitive Transposed Series-Parallel Topology With Fine Tuning Capabilities , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Yogesh K. Ramadass.  Energy processing circuits for low-power applications , 2009 .

[8]  Michiel Steyaert,et al.  A 82% efficiency 0.5% ripple 16-phase fully integrated capacitive voltage doubler , 2009, 2009 Symposium on VLSI Circuits.

[9]  A.P. Chandrakasan,et al.  Voltage Scalable Switched Capacitor DC-DC Converter for Ultra-Low-Power On-Chip Applications , 2007, 2007 IEEE Power Electronics Specialists Conference.

[10]  K. McStay,et al.  Scaling deep trench based eDRAM on SOI to 32nm and Beyond , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[11]  Pingqiang Zhou,et al.  Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[12]  Robert H. Dennard,et al.  Practical Strategies for Power-Efficient Computing , 2010 .

[13]  Vivek De,et al.  Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[14]  Phillip Stanley-Marbell,et al.  Pinned to the walls — Impact of packaging and application properties on the memory and power walls , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[15]  Robert H. Dennard,et al.  Practical Strategies for Power-Efficient Computing Technologies , 2010, Proceedings of the IEEE.

[16]  Michael D. Seeman,et al.  A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).