유전자 알고리즘을 이용하여 설계된 ECC회로의 uniform distribution memory data에서의 성능 분석

This paper shows a performance analysis of the ECC circuit which is designed by genetic algorithm for reducing power consumption. In single-error correcting, double error-detecting checker circuits, the power is minimized with little or no impact on area and delay, using the degrees of freedom in selecting the parity check matrix of the error correcting codes. The genetic algorithm is employed to solve the non-linear power optimization problem. The method is applied to two commonly used SEC-DED codes: Hamming and odd column weight Hsiao codes. Experiments are performed to show the performance of the proposed method.