A Compact Transactional Memory Multiprocessor System on FPGA

In this paper we present a rapid prototyping platform on a single Field Programmable Gate Array (FPGA) with support for software transactional memory. The system is composed only by off-the-shelf cores and is useful for porting and early validation of programs to the transactional memory programming model. We discuss the implementation of the software layer of this platform, propose an analysis of the system and compare it to a hardware lock based multiprocessor architecture, showing the trade-offs in terms of performance and programming complexity.

[1]  Mark L. Chang,et al.  Low-Cost Stereo Vision on an FPGA , 2007 .

[2]  Kunle Olukotun,et al.  ATLAS: A Chip-Multiprocessor with Transactional Memory Support , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[3]  Christoforos Kachris,et al.  Configurable Transactional Memory , 2007, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007).

[4]  Gianluca Palermo,et al.  A design kit for a fully working shared memory multiprocessor on FPGA , 2007, GLSVLSI '07.

[5]  Maurice Herlihy,et al.  Transactional Memory: Architectural Support For Lock-free Data Structures , 1993, Proceedings of the 20th Annual International Symposium on Computer Architecture.