Impact of interconnect parameter variations on wire-tree delay

Abstract New distributed wire-tree and stochastic delay distribution models are proposed to assess the impact of interconnect process parameter variations on fluctuations in interconnect delay. Closed-form expressions for distributed wire-tree delay reported are accurate to within 5% of HSPICE simulations. These are used in tandem with stochastic models for delay distributions to estimate deviations in interconnect delay. Deviations in interconnect delay are reported to increase as the square of interconnect length and inversely with interconnect width. Introduction With scaling of minimum feature size, although interconnect delay increases can be limited to 30% per generation by reverse scaling of metal and insulator dimensions [1], interconnect delay and variations in interconnect delay increasingly limit chip speed and delay variation margins [2,3,4]. While interconnect delay imposes constraints on maximum interconnect length, variations in interconnect delay that increase sharply at smaller line widths [5] also impose constraints on minimum interconnect width along RC limited paths. Accurately estimating interconnect delays and variations in interconnect delay along arbitrary wire tree networks, due to interconnect parameter variations is thus essential to optimizing wire geometries and repeater circuitry along RC limited paths. First-order path-tracing RC tree methods [6] based on the Elmore delay model [7] lack in accuracy in estimating delays across distributed wire-tree networks. The Q order and more accurate Asymptotic Waveform Evaluation (AWE) extensions [8,9] require formulating and solving nodal matrices where computational effort and memory requirements increase with chip and wire-tree complexity even though these techniques are more efficient than realtime HSPICE simulations. Recent attempts to estimate the impact of interconnect process variations on clock skew and interconnect delay [3] employ Monte Carlo simulations using a finite-difference solver. Any of the above methodologies to estimate wire-tree delay and/or variations in wire-tree delay would incur increasing costs in accuracy or in computational time and effort with increase in chip and interconnect complexity. Sakurai’s accurate (<3% error) closed-form analytical models for distributed interconnect delay [10] that apply only to the case of step excitations at the input of a buffer driving a 2-pin net are extended in this work to the more commonly encountered and complex cases