The design and implementation of reconfigurable multiplier with high flexibility

This paper presents a reconfigurable mechanism for the multiplier. The proposed mechanism is applied to generate a multiplier, whose data width, type and pipeline depth can be customized. The data width of each operand of these generated multipliers can be configured for 4i where i=1, 2, 3, 4, 5, 6, 7, 8. And the data type of operand can be unsigned or signed at will. The multiplier is composed of the smallest multiplier-cells, the 4bit multiplier. Synthesized results could reach as high as 425.53MHz using SMIC 0.13um CMOS technology library under the worst case condition.