Performance analysis of dual-k spacer at source side for underlap FinFETs

This paper proposes an overall improvement in performance of Gate-Source/Drain underlap FinFET structure by introducing the concept of dual-k spacer between gate and source. By optimizing the underlap length, we demonstrate the sensitivity of dual-k spacer width. We analyze that the variation in width of high-k presents a noticeable improvements in On-Off current ratio (Ion/Ioff). The proposed structure is verified by TCAD simulations of underlap FinFET device with varying device physical parameters such as spacer width, spacer material etc. and optimizes the width of the high-k and low-k spacer. The proposed device architecture enhances gate control over channel and can be used to design low power digital circuits.

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