Analysis of topography effects on lithographic performance in double patterning applications

Double Patterning (DP) is considered the most viable solution for printing features of the 32nm technology node using 193nm immersion lithography. Independent of the approach of the DP implementation (be it Litho-Etch-Litho-Etch or Litho-Process-Litho-Etch), the second lithography step is influenced by the underlying topography on the wafer. Given the tight constraints on the process, an accurate prediction of the impact of the embedded topography on critical features is inevitable to meet the design requirements of the corresponding device layer. In this paper we use rigorous simulations of the electro-magnetic field distribution to quantify the effect of wafer topography on the second lithography step. In particular, we investigate the impact of the topography on CD control and corresponding process windows for typical 1D patterns. The influence of non-flat BARC, non-flat resist surfaces, hard mask material and process variations in the first litho step is simulated for dual line as well as dual trench processes. A metric to quantify standing waves in resist is introduced and used to optimize BARC thickness. Further, we investigate typical 2D clips of decomposed mask layouts relevant for the 32nm node. The simulation methodology and algorithm performance are presented, in particular with respect to its distributed computing capabilities.