Formal Modeling of Timed Function Blocks for the Automatic Verification of Ladder Diagram Programs

We describe our approach to the automated verification of Lad der Diagrams programs. This combines a formal semantics for a large fragment of the LD language (including a modeling of timed function blocks), and a powerful temporal logic model checking technology.

[1]  Bruce H. Krogh,et al.  Formal verification of PLC programs , 1998, Proceedings of the 1998 American Control Conference. ACC (IEEE Cat. No.98CH36207).

[2]  Kenneth L. McMillan,et al.  Symbolic model checking , 1992 .

[3]  Hanno Wupper,et al.  Timed automaton models for simple programmable logic controllers , 1999, Proceedings of 11th Euromicro Conference on Real-Time Systems. Euromicro RTS'99.

[4]  Alexander Aiken,et al.  Detecting Races in Relay Ladder Logic Programs , 1998, TACAS.

[5]  Rajeev Alur,et al.  A Theory of Timed Automata , 1994, Theor. Comput. Sci..

[6]  Adam L. Turk,et al.  Verification of Real Time Chemical Processing Systems , 1997, HART.

[7]  I. Moon.  Modeling programmable logic controllers for logic verification , 1994, IEEE Control Systems.

[8]  E. Allen Emerson,et al.  Temporal and Modal Logic , 1991, Handbook of Theoretical Computer Science, Volume B: Formal Models and Sematics.