Design and Implementation of SORIGA-optimized Powers-of-two FIR Filter on FPGA

With the introduction of sophisticated algorithms, the field of signal processing has experienced enormous diversification of late. In addition to this, design of hardware efficient digital systems has grown sufficient interest amongst the researchers in recent past. In this article, an attempt has been made to realize hardware friendly powers-of-two FIR filter by using an evolutionary computation, called Self-organizing Random Immigrants Genetic Algorithm (SORIGA). In connection to this, this work makes one comparative study amongst various multiplier-less FIR filters in terms of hardware complexity when implemented on an FPGA chip. Finally, supremacy of the proposed design has firmly been established by comparing its hardware cost with many of the state-of-the-art powers-of-two FIR filters.

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