Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant
暂无分享,去创建一个
[1] A. Visconti,et al. Random Telegraph Noise Effect on the Programmed Threshold-Voltage Distribution of Flash Memories , 2009, IEEE Electron Device Letters.
[2] Andrea L. Lacaita,et al. Reviewing the Evolution of the NAND Flash Technology , 2017, Proceedings of the IEEE.
[3] Kinam Kim,et al. Effects of interface trap generation and annihilation on the data retention characteristics of flash memory cells , 2004 .
[4] A. Lacaita,et al. Investigation and Compact Modeling of the Time Dynamics of the GIDL-Assisted Increase of the String Potential in 3-D NAND Flash Arrays , 2018, IEEE Transactions on Electron Devices.
[5] Jonghoon Park,et al. 7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).
[6] T. Melde,et al. Analysis of trap mechanisms responsible for Random Telegraph Noise and erratic programming on sub-50nm floating gate flash memories , 2009, 2009 10th Annual Non-Volatile Memory Technology Symposium (NVMTS).
[7] Myounggon Kang,et al. Down-Coupling Phenomenon of Floating Channel in 3D NAND Flash Memory , 2016, IEEE Electron Device Letters.
[8] Dong Woo Kim,et al. Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory , 2006, 2009 Symposium on VLSI Technology.
[9] Andrea L. Lacaita,et al. Revisiting Charge Trapping/Detrapping in Flash Memories From a Discrete and Statistical Standpoint—Part II: On-Field Operation and Distributed-Cycling Effects , 2014, IEEE Transactions on Electron Devices.
[10] Carmine Miccoli,et al. Time dependent threshold-voltage fluctuations in NAND flash memories: From basic physics to impact on array operation , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).
[11] Alessandro Calderoni,et al. Effect of Floating-Gate Polysilicon Depletion on the Erase Efficiency of nand Flash Memories , 2010, IEEE Electron Device Letters.
[12] Shinsugita-cho Isogo-ku,et al. Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory , 2007 .
[13] K. Otsuga,et al. The Impact of Random Telegraph Signals on the Scaling of Multilevel Flash Memories , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..
[14] Su-Jin Ahn,et al. Evolution of NAND Flash Memory: From 2D to 3D as a Storage Market Leader , 2017, 2017 IEEE International Memory Workshop (IMW).
[15] Jae-Duk Lee,et al. A New Programming Disturbance Phenomenon in NAND Flash Memory By Source/Drain Hot-Electrons Generated By GIDL Current , 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.
[16] Investigation of the undershoot effect in polycrystalline silicon thin film transistors , 2008 .
[17] R. Shirota,et al. Analysis of the Correlation Between the Programmed Threshold-Voltage Distribution Spread of nand Flash Memory Devices and Floating-Gate Impurity Concentration , 2011, IEEE Transactions on Electron Devices.
[18] Xingqi Zou,et al. A Novel Program Scheme for Program Disturbance Optimization in 3-D NAND Flash Memory , 2018, IEEE Electron Device Letters.
[19] Eun-seok Choi,et al. Device considerations for high density and highly reliable 3D NAND flash cell in near future , 2012, 2012 International Electron Devices Meeting.
[20] A.L. Lacaita,et al. Statistical Model for Random Telegraph Noise in Flash Memories , 2008, IEEE Transactions on Electron Devices.
[21] Onur Mutlu,et al. Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery , 2015, 2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks.
[22] C.M. Compagnoni,et al. Analytical Model for the Electron-Injection Statistics During Programming of Nanoscale nand Flash Memories , 2008, IEEE Transactions on Electron Devices.
[23] Byung-Gook Park,et al. Effect of traps on transient bit-line current behavior in word-line stacked nand flash memory with poly-Si body , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
[24] H. Belgal,et al. Recovery Effects in the Distributed Cycling of Flash Memories , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.
[25] A. Visconti,et al. Ultimate Accuracy for the nand Flash Program Algorithm Due to the Electron Injection Statistics , 2008, IEEE Transactions on Electron Devices.
[26] Junhee Lim,et al. A new ruler on the storage market: 3D-NAND flash for high-density memory and its technology evolutions and challenges on the future , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).
[27] Kyungmin Kim,et al. A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).
[28] Christian Monzio Compagnoni,et al. Investigation of the Random Telegraph Noise Instability in Scaled Flash Memory Arrays , 2008 .
[29] Jin-Ki Kim,et al. A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.
[30] A. Lacaita,et al. Investigation of the RTN Distribution of Nanoscale MOS Devices From Subthreshold to On-State , 2013, IEEE Electron Device Letters.
[31] A. Goda,et al. Scaling Trends in NAND Flash , 2018, 2018 IEEE International Electron Devices Meeting (IEDM).
[32] A. Visconti,et al. Threshold-Voltage Instability Due to Damage Recovery in Nanoscale NAND Flash Memories , 2011, IEEE Transactions on Electron Devices.
[33] Krishna Parat,et al. A floating gate based 3D NAND technology with CMOS under array , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).
[34] J. Kessenich,et al. Bit error rate in NAND Flash memories , 2008, 2008 IEEE International Reliability Physics Symposium.
[35] Dick James. Recent advances in memory technology , 2013, ASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference.
[36] Carmine Miccoli,et al. Temperature Effects in NAND Flash Memories: A Comparison Between 2-D and 3-D Arrays , 2017, IEEE Electron Device Letters.
[37] Kuo-Pin Chang,et al. Study of fast initial charge loss and it's impact on the programmed states Vt distribution of charge-trapping NAND Flash , 2010, 2010 International Electron Devices Meeting.
[38] A. Visconti,et al. Comprehensive Analysis of Random Telegraph Noise Instability and Its Scaling in Deca–Nanometer Flash Memories , 2009, IEEE Transactions on Electron Devices.
[39] Andrea L. Lacaita,et al. Variability effects on the VT distribution of nanoscale NAND Flash memories , 2010, 2010 IEEE International Reliability Physics Symposium.
[40] Massimo Rossini,et al. A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[41] A. Visconti,et al. Defects spectroscopy in SiO2 by statistical random telegraph noise analysis , 2006, 2006 International Electron Devices Meeting.
[42] Chih-Yuan Lu,et al. Polycrystalline-silicon channel trap induced transient read instability in a 3D NAND flash cell string , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).
[43] Jungdal Choi,et al. Effects of floating-gate interference on NAND flash memory cell operation , 2002 .
[44] Hyungcheol Shin,et al. The Air Spacer Technology for Improving the Cell Distribution in 1 Giga Bit NAND Flash Memory , 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.
[45] P. Kalavade,et al. Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling , 2004, IEEE Transactions on Device and Materials Reliability.
[46] Takamaro Kikkawa,et al. Scaling challenge of Self-Aligned STI cell (SA-STI cell) for NAND flash memories , 2013 .
[47] C. Hu,et al. Stress-induced current in thin silicon dioxide films , 1992, 1992 International Technical Digest on Electron Devices Meeting.
[48] Krishna Parat,et al. 25nm 64Gb MLC NAND technology and scaling challenges invited paper , 2010, 2010 International Electron Devices Meeting.
[49] A. Lacaita,et al. First evidence for injection statistics accuracy limitations in NAND Flash constant-current Fowler-Nordheim programming , 2007, 2007 IEEE International Electron Devices Meeting.
[50] Piero Olivo,et al. Erratic bits in Flash memories under Fowler-Nordheim programming , 2002 .
[51] S M Amoroso,et al. Three-Dimensional Simulation of Charge-Trap Memory Programming—Part II: Variability , 2011, IEEE Transactions on Electron Devices.
[52] R. E. Shiner,et al. A new reliability model for post-cycling charge retention of flash memories , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).
[53] Neal R. Mielke,et al. Reliability of Solid-State Drives Based on NAND Flash Memory , 2017, Proceedings of the IEEE.
[54] Andrea L. Lacaita,et al. Revisiting Charge Trapping/Detrapping in Flash Memories From a Discrete and Statistical Standpoint—Part I: \(V_{T}\) Instabilities , 2014, IEEE Transactions on Electron Devices.
[55] Andrea L. Lacaita,et al. New technique for fast characterization of SILC distribution in flash arrays , 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).
[56] Byungseok Lee,et al. A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies , 2011, 2011 International Electron Devices Meeting.
[57] Tatsuya Shimoda,et al. Switch-on transient behavior in low-temperature polycrystalline silicon thin-film transistors , 2000 .
[58] Andrea L. Lacaita,et al. A statistical model for SILC in flash memories , 2002 .
[59] Ki-Hong Lee,et al. Inherent Issues and Challenges of Program Disturbance of 3D NAND Flash Cell , 2012, 2012 4th IEEE International Memory Workshop.
[60] R. Shirota,et al. Extended data retention process technology for highly reliable flash EEPROMs of 10/sup 6/ to 10/sup 7/ W/E cycles , 1998, 1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173).
[61] G. M. Paolucci,et al. Characterization and Modeling of Temperature Effects in 3-D NAND Flash Arrays—Part I: Polysilicon-Induced Variability , 2018, IEEE Transactions on Electron Devices.
[62] Andrea L. Lacaita,et al. Comprehensive investigation of the impact of lateral charge migration on retention performance of planar and 3D SONOS devices , 2012 .
[63] A. Spinelli,et al. Impact of Cycling on Random Telegraph Noise in 3-D NAND Flash Arrays , 2018, IEEE Electron Device Letters.
[64] Jai Hyuk Song,et al. 32nm 3-bit 32Gb NAND Flash Memory with DPT (d̲ouble p̲atterning t̲echnology) process for mass production , 2010, 2010 Symposium on VLSI Technology.
[65] Xingqi Zou,et al. A Novel Read Scheme for Read Disturbance Suppression in 3D NAND Flash Memory , 2017, IEEE Electron Device Letters.
[66] A. Hikavyy,et al. First demonstration of monocrystalline silicon macaroni channel for 3-D NAND memory devices , 2018, 2018 IEEE Symposium on VLSI Technology.
[67] Gyoyoung Jin,et al. Scaling and reliability of NAND flash devices , 2014, 2014 IEEE International Reliability Physics Symposium.
[68] J. Van Houdt,et al. Impact of lateral charge migration on the retention performance of planar and 3D SONOS devices , 2011, 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC).
[69] G. M. Paolucci,et al. Characterization and Modeling of Temperature Effects in 3-D NAND Flash Arrays—Part II: Random Telegraph Noise , 2018, IEEE Transactions on Electron Devices.
[70] C. Hu,et al. Random telegraph noise in flash memories - model and technology scaling , 2007, 2007 IEEE International Electron Devices Meeting.
[71] R. Fontana,et al. Moore’s law realities for recording systems and memory storage components: HDD, tape, NAND, and optical , 2018 .
[72] Hiroshi Nakamura,et al. 13.5 A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).
[73] Y. Iwata,et al. Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory , 2007, 2007 IEEE International Electron Devices Meeting.
[74] Byung-Gook Park,et al. Suppression of Read Disturb Fail Caused by Boosting Hot Carrier Injection Effect for 3-D Stack NAND Flash Memories , 2014, IEEE Electron Device Letters.
[75] Byung-Gook Park,et al. Comprehensive analysis of retention characteristics in 3-D NAND flash memory cells with tube-type poly-Si channel structure , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).
[76] Sung-Jin Choi,et al. Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3-D NAND flash memory , 2016, 2016 IEEE Symposium on VLSI Technology.
[77] Angelo Visconti,et al. Cycling-Induced Charge Trapping/Detrapping in Flash Memories—Part II: Modeling , 2016, IEEE Transactions on Electron Devices.
[78] Xu Li,et al. A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).
[79] Angelo Visconti,et al. Cycling-Induced Charge Trapping/Detrapping in Flash Memories—Part I: Experimental Evidence , 2016, IEEE Transactions on Electron Devices.
[80] R. Bez,et al. What we have learned on flash memory reliability in the last ten years , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
[81] Andrea L. Lacaita,et al. Investigation of the programming accuracy of a double-verify ISPP algorithm for nanoscale NAND Flash memories , 2011, 2011 International Reliability Physics Symposium.
[82] Keonsoo Kim,et al. Direct Field Effect of Neighboring Cell Transistor on Cell-to-Cell Interference of nand Flash Cell Arrays , 2009, IEEE Electron Device Letters.
[83] Wook-Ghee Hahn,et al. A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate , 2016, IEEE Journal of Solid-State Circuits.