An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology

In this paper, we present D flip-flop, Quatro, and stacked Quarto flip-flop designs fabricated in a commercial 28-nm CMOS FDSOI technology. Stacked-transistor structures are introduced in the stacked Quatro design to protect the sensitive devices of the original structure. Striking either of the stacked devices will not upset the latch because the conduction path to the supply rail is still cut off by the other off-state device. The irradiation experimental results substantiate that the stacked Quatro design has significantly better SEU tolerance (e.g., higher heavy ion upset Linear Energy Transfer threshold and smaller cross-section data) than the reference designs. It introduces power and area penalties because the proposed design duplicates and stacks two sensitive PMOS devices. Additionally, the impact of technology scaling on Quatro in various technology nodes (130-nm, 65-nm, and 40-nm) has been studied suggesting decreasing upset threshold and decreasing cross-section data.

[1]  J. S. Kauppila,et al.  Utilizing device stacking for area efficient hardened SOI flip-flop designs , 2014, 2014 IEEE International Reliability Physics Symposium.

[2]  M. Nicolaidis,et al.  Design for soft error mitigation , 2005, IEEE Transactions on Device and Materials Reliability.

[3]  M. L. Alles,et al.  Technology scaling and soft error reliability , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[4]  Lloyd W. Massengill,et al.  Basic mechanisms and modeling of single-event upset in digital microelectronics , 2003 .

[5]  P. Marshall,et al.  32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches , 2011, IEEE Transactions on Nuclear Science.

[6]  B. L. Bhuva,et al.  Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology , 2016, IEEE Transactions on Nuclear Science.

[7]  S. Jahinuzzaman,et al.  A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability , 2009, IEEE Transactions on Nuclear Science.

[8]  Li Chen,et al.  Supply Voltage Dependence of Heavy Ion Induced SEEs on 65 nm CMOS Bulk SRAMs , 2015, IEEE Transactions on Nuclear Science.

[9]  H. Asai,et al.  Optimization for SEU/SET Immunity on 0.15 $\mu$m Fully Depleted CMOS/SOI Digital Logic Devices , 2006, IEEE Transactions on Nuclear Science.

[10]  Ethan H. Cannon,et al.  Robust SEU Mitigation of 32 nm Dual Redundant Flip-Flops Through Interleaving and Sensitive Node-Pair Spacing , 2013, IEEE Transactions on Nuclear Science.

[11]  S. Cristoloveanu,et al.  Extraction of the Parasitic Bipolar Gain Using the Back-Gate in Ultrathin FD SOI MOSFETs , 2015, IEEE Electron Device Letters.

[12]  J. S. Kauppila,et al.  Heavy Ion SEU Test Data for 32nm SOI Flip-Flops , 2015, 2015 IEEE Radiation Effects Data Workshop (REDW).

[13]  R. Wong,et al.  Single-Event Tolerant Flip-Flop Design in 40-nm Bulk CMOS Technology , 2011, IEEE Transactions on Nuclear Science.

[14]  Robert Baumann,et al.  Soft errors in advanced computer systems , 2005, IEEE Design & Test of Computers.

[15]  B. L. Bhuva,et al.  Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections , 2013, IEEE Transactions on Nuclear Science.

[16]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[17]  H.-B Wang,et al.  An Area Efficient SEU-Tolerant Latch Design , 2014, IEEE Transactions on Nuclear Science.

[18]  Robert C. Aitken,et al.  Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[19]  Marty R. Shaneyfelt,et al.  Impact of technology trends on SEU in CMOS SRAMs , 1996 .