Design of an on-interposer passive equalizer embedded on a ground plane for 30Gbps serial data transmission

In this paper, a new on-interposer passive equalizer was proposed for chip-to-chip high-speed serial data transmission. It is a coil-shaped shunt metal line and embedded on a ground plane to maximize channel routability. Since the proposed equalizer is based on the fine pitch design rules of silicon interposer, it can be integrated in a small area. Equalizing method is based on a high pass filter composed of an inductance and a resistance of the proposed structure. It achieves wide-band equalization up to data rate of 30 Gbps. Performance of the proposed equalizer is verified using frequency- and time-domain simulation. By applying the proposed equalizer to 30 Gbps channel, eye-height was improved by 13.4 % of input voltage and timing jitter was reduced by 5.5 % of one unit interval.

[1]  Joungho Kim,et al.  A compact on-interposer passive equalizer for chip-to-chip high-speed data transmission , 2012, 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems.

[2]  Mark Horowitz,et al.  High-speed electrical signaling: overview and limitations , 1998, IEEE Micro.

[3]  Young-Hyun Jun,et al.  A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $\times$ 128 I/Os Using TSV Based Stacking , 2011, IEEE Journal of Solid-State Circuits.

[4]  Young-Hyun Jun,et al.  A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking , 2011, 2011 IEEE International Solid-State Circuits Conference.

[5]  S. Gowda,et al.  A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology , 2006, IEEE Journal of Solid-State Circuits.

[6]  Jri Lee,et al.  A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology , 2010, IEEE Journal of Solid-State Circuits.