An Experimental Perspective of Trap Generation Under BTI Stress

A gated-diode or direct current IV method is used to characterize trap generation (TG) under negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) stress in different planar high-k metal gate p-channel and n-channel MOSFETs, respectively. After correction of the measurement delay, very similar time (tSTR), voltage (VG,STR), temperature (T), AC pulse duty cycle, and frequency ( f ) dependence of TG is seen for NBTI and PBTI. Measured TG shows power-law time dependence with a time exponent of n ~ 0.16 for NBTI and PBTI and for DC and AC stress. Uncoupled nature of voltage acceleration (Γ) and T activation (EA) is seen. Interlayer scaling has a similar impact on EA and Γ for NBTI and PBTI. However, the physical location of TG is shown to be different for NBTI and PBTI stress.

[1]  Andreas Kerber,et al.  Stress-induced leakage current and defect generation in nFETs with HfO2/TiN gate stacks during positive-bias temperature stress , 2009, 2009 IEEE International Reliability Physics Symposium.

[2]  F. Nouri,et al.  On the dispersive versus arrhenius temperature activation of nbti time evolution in plasma nitrided gate oxides: measurements, theory, and implications , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[3]  E. Cartier,et al.  Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks , 2009, IEEE Transactions on Device and Materials Reliability.

[4]  A. Rahman,et al.  Intrinsic transistor reliability improvements from 22nm tri-gate technology , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[5]  M. Alam,et al.  A Comparative Study of Different Physics-Based NBTI Models , 2013, IEEE Transactions on Electron Devices.

[6]  A. Brand,et al.  HKMG process impact on N, P BTI: Role of thermal IL scaling, IL/HK integration and post HK nitridation , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[7]  S. Mahapatra,et al.  Universality of NBTI - From devices to circuits and products , 2014, 2014 IEEE International Reliability Physics Symposium.

[8]  S. Mahapatra,et al.  Trap Generation in IL and HK layers during BTI / TDDB stress in scaled HKMG N and P MOSFETs , 2014, 2014 IEEE International Reliability Physics Symposium.

[9]  J. Cai,et al.  Monitoring interface traps by DCIV method , 1999 .

[10]  SILC-based reassignment of trapping and trap generation regimes of positive bias temperature instability , 2011, 2011 International Reliability Physics Symposium.

[11]  V. Huard.  Two independent components modeling for Negative Bias Temperature Instability , 2010, 2010 IEEE International Reliability Physics Symposium.

[12]  P. Nicollian,et al.  Material dependence of hydrogen diffusion: implications for NBTI degradation , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[13]  X. Garros,et al.  Large-Scale Time Characterization and Analysis of PBTI In HFO2/Metal Gate Stacks , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[14]  Y. Mitani.  Influence of nitrogen in ultra-thin SiON on negative bias temperature instability under AC stress , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[15]  Gennadi Bersuker,et al.  Applications of DCIV method to NBTI characterization , 2007, Microelectron. Reliab..

[16]  S. Deora,et al.  A critical re-evaluation of the usefulness of R-D framework in predicting NBTI stress and recovery , 2011, 2011 International Reliability Physics Symposium.

[17]  M.A. Alam,et al.  Separation method of hole trapping and interface trap generation and their roles in NBTI reaction-diffusion model , 2008, 2008 IEEE International Reliability Physics Symposium.

[18]  M. Nelhiebel,et al.  A two-stage model for negative bias temperature instability , 2009, 2009 IEEE International Reliability Physics Symposium.

[19]  T. Grasser,et al.  Understanding and modeling AC BTI , 2011, 2011 International Reliability Physics Symposium.

[20]  M. Nelhiebel,et al.  Understanding negative bias temperature instability in the context of hole trapping (Invited Paper) , 2009 .

[21]  S. Mahapatra,et al.  A comprehensive DC/AC model for ultra-fast NBTI in deep EOT scaled HKMG p-MOSFETs , 2014, 2014 IEEE International Reliability Physics Symposium.

[22]  G. Dewey,et al.  BTI reliability of 45 nm high-K + metal-gate process technology , 2008, 2008 IEEE International Reliability Physics Symposium.

[23]  S. Mahapatra,et al.  A consistent physical framework for N and P BTI in HKMG MOSFETs , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[24]  G. Bersuker,et al.  Experimental Evidence of the Fast and Slow Charge Trapping/Detrapping Processes in High- k Dielectrics Subjected to PBTI Stress , 2008, IEEE Electron Device Letters.

[25]  K. Ahmed,et al.  On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy? , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[26]  T. Grasser,et al.  The Universality of NBTI Relaxation and its Implications for Modeling and Characterization , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[27]  Souvik Mahapatra,et al.  A Detailed Study of Gate Insulator Process Dependence of NBTI Using a Compact Model , 2014, IEEE Transactions on Electron Devices.