Modeling double gate FinFETs by using artificial neural network
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[1] Mark S. Lundstrom,et al. The ballistic nanotransistor: a simulation study , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
[2] Keunwoo Kim,et al. Double-gate CMOS: symmetrical- versus asymmetrical-gate devices , 2001 .
[3] Stephen A. Billings,et al. Radial basis function network configuration using genetic algorithms , 1995, Neural Networks.
[4] Mohan Vamsi Dunga,et al. Nanoscale CMOS modeling , 2008 .
[5] C. Jungemann,et al. Efficient Full-Band Monte Carlo Simulation of Silicon Devices , 1999 .
[6] T. Tezuka,et al. Control of threshold-voltage and short-channel effects in ultrathin strained-SOI CMOS devices , 2005, IEEE Transactions on Electron Devices.
[7] Yuan Taur,et al. Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.
[8] S. Venkatesan,et al. Techniques for reducing the reverse short channel effect in sub-0.5 μm CMOS , 1995, IEEE Electron Device Letters.
[9] D. Jovanovic,et al. Computational techniques for the nonequilibrium quantum field theory simulation of MOSFETs , 2000, 7th International Workshop on Computational Electronics. Book of Abstracts. IWCE (Cat. No.00EX427).
[10] Andrzej Cichocki,et al. Neural networks for optimization and signal processing , 1993 .