Low power VLSI compressors

We present a new design for a 1-bit full adder featuring hybrid-CMOS design style. Our approach achieves low-energy operations in 180nm technology. The proposed new SERF- full adder (FA) circuit optimized for ultra low power operation is based on modified XNOR gates with clock gating to minimize the power consumption. And also generates full-swing outputs simultaneously. During our simulations, we arrived at the conclusion that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The new adder displayed better power and delay metrics as compared to the standard full adders. To evaluate the performance of the new full adder in a real circuit, we realized 4-2,5-2,5-3,7-2,11-2,15-4,31-5 compressors which are basically used in multiplier modules of DSP filters. Compressor using blockwise power shut down technique is implemented. Simulated results using 180nm CMOS technology are provided. The 32×32 bit MAC unit using proposed full adder without block wise shut down technique produced a power saving of 24.27% over 32 bit MAC designed using SERF full adder and 35.07% power savings over 32 bit MAC designed using conventional 28T full adder.

[1]  Weng Fook Lee.  VHDL Coding and Logic Synthesis with Synopsys , 2000 .

[2]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[3]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[4]  B. Leupen,et al.  Design and analysis , 1997 .

[5]  Keshab K. Parhi.  Fast low-energy VLSI binary addition , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[6]  Chip-Hong Chang,et al.  Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

[7]  Wang Ling Goh,et al.  Ultra low-power full-adder for biomedical applications , 2009, 2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC).

[8]  Tarek Darwish,et al.  Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Z. Abid,et al.  Low power n-bit adders and multiplier using lowest-number-of-transistor 1-bit adders , 2005, Canadian Conference on Electrical and Computer Engineering, 2005..

[10]  G. M. Blair.  Designing low-power digital CMOS , 1994 .

[11]  Edwin Hsing-Mean Sha,et al.  A novel multiplexer-based low-power full adder , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

[12]  Magdy Bayoumi,et al.  A novel high-performance CMOS 1-bit full-adder cell , 2000 .

[13]  Lizy Kurian John,et al.  A novel low power energy recovery full adder cell , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[14]  Lingamneni Avinash,et al.  Novel architectures for efficient (m, n) parallel counters , 2007, GLSVLSI '07.

[15]  Farshad Moradi,et al.  Ultra low power full adder topologies , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[16]  James E. Gunn,et al.  A low-power DSP core-based software radio architecture , 1999, IEEE J. Sel. Areas Commun..

[17]  Nestoras Tzartzanis,et al.  Design and analysis of a low-power energy-recovery adder , 1995, Proceedings. Fifth Great Lakes Symposium on VLSI.

[18]  Mohamed I. Elmasry,et al.  Circuit techniques for CMOS low-power high-performance multipliers , 1996 .