Hole mobility improvement in silicon-on-insulator and bulk silicon transistors using local strain

Summary form only given. Improvements in transport properties through strain have been demonstrated in the operating characteristics of field-effect transistors in the Ga/sub 1-x/In/sub x/As/GaAs and the SiGe/Si system. For CMOS, an improvement in p-channel device characteristics is desirable, and the hole mobility is an appropriate tool for attaining it. Si on relaxed SiGe is one system where such an improvement occurs and has been observed. Here, we discuss how changes in mobility and p-channel device properties can be deliberately made in silicon and silicon-on-insulator (SOI) structures through the introduction of local strain and without a major change in the underlying isolation techniques. Effective mobility changes of up to 40% have been observed for device widths of 1 /spl mu/m in silicon-on-insulator structures.