A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded $\Sigma \Delta$ Modulator

Although SigmaDelta modulators have largely been implemented as discrete-time (DT) circuits, a continuous-time (CT) approach offers significant advantages for realizing high-accuracy A/D converters at signal bandwidths where technology considerations may impose significant constraints. A CT design allows for relaxed amplifier unity-gain frequency and power requirements, which can enable the realization of high-resolution modulators with bandwidths of several MHz or more at low power. It also provides the advantage of inherent anti-aliasing filtering. This paper introduces a hybrid CT/DT SigmaDelta modulator for A/D conversion that combines the benefits of CT and DT circuits, while mitigating the challenges associated with CT design. The second-order first stage of a two-stage cascade is implemented in CT, while the first-order second stage is a DT circuit. An experimental prototype of the proposed modulator, integrated in 0.18-mum CMOS technology, operates from a 1.2-V analog supply to allow for easier migration to a 0.13-mum or 90-nm CMOS technology. The prototype achieves a dynamic range of 77 dB, a peak SNR of 71 dB, a peak SNDR of 67 dB, and worst-case anti-aliasing filtering of 48 dB for a signal bandwidth of 7.5 MHz and a sampling rate of 240 MHz. The total power dissipation is 89 mW, including 63.6 mW of analog power.

[1]  E. Sanchez-Sinencio,et al.  A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth , 2004, IEEE Journal of Solid-State Circuits.

[2]  Bruce A. Wooley,et al.  A third-order sigma-delta modulator with extended dynamic range , 1994 .

[3]  Bas M. Putter A 5,sup>th-order CT/DT Multi-Mode ΔΣ Modulator , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  C. Holuigue,et al.  A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB , 2006, IEEE Journal of Solid-State Circuits.

[5]  E.J. van der Zwan,et al.  A 0.2 mW CMOS /spl Sigma//spl Delta/ modulator for speech coding with 80 dB dynamic range , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[6]  T. Burger,et al.  A 13.5mW, 185 MSample/s /spl Delta//spl Sigma/-modulator for UMTS/GSM dual-standard IF reception , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[7]  L.J. Breems,et al.  A cascaded continuous-time /spl Sigma//spl Delta/ modulator with 67dB dynamic range in 10MHz bandwidth , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[8]  E. Sánchez-Sinencio,et al.  A Continuous-Time Modulator With 88-dB Dynamic Range and 1 . 1-MHz Signal Bandwidth , 2001 .

[9]  E. Sánchez-Sinencio,et al.  A continuous-time /spl Sigma//spl Delta/ modulator with 88dB dynamic range and 1.1MHz signal bandwidth , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[10]  Van Der Zwan A 0.2-mW CMOS ΣΔ modulator for speech coding with 80 dB dynamic range , 1996 .

[11]  Philippe Bénabès,et al.  A methodology for designing continuous-time sigma-delta modulators , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[12]  A. Wiesbauer,et al.  A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13/spl mu/m CMOS , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[13]  Michiel Steyaert,et al.  A Design-Optimized Continuous-Time Delta–Sigma ADC for WLAN Applications , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  Bruce A. Wooley,et al.  Second-order sigma-delta modulation for digital-audio signal acquisition , 1991 .

[15]  Saska Lindfors,et al.  80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers , 2003 .

[16]  R. Schreier,et al.  Delta-sigma modulators employing continuous-time circuitry , 1996 .

[17]  James C. CAhY A Use of Double Integration in Sigma Delta Modulation , 1985 .

[18]  Thomas Burger,et al.  A 13.5mW, 185 MSample/s ΔΣ-modulator for UMTS/GSM dual-standard IF reception , 2001 .

[19]  W. Snelgrove,et al.  Excess loop delay in continuous-time delta-sigma modulators , 1999 .

[20]  Gabor C. Temes,et al.  The Design of Cascaded ADCs , 1997 .

[21]  B.A. Wooley,et al.  A 1.2-V 77-dB 7.5-MHz Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator , 2007, 2007 IEEE Symposium on VLSI Circuits.

[22]  L.J. Breems,et al.  A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth , 2004, IEEE Journal of Solid-State Circuits.

[23]  P.K. Hanumolu,et al.  A 0.8-V accurately tuned linear continuous-time filter , 2005, IEEE Journal of Solid-State Circuits.

[24]  J. Vink,et al.  A CMOS multi-bit sigma-delta modulator for video applications , 1998, Proceedings of the 24th European Solid-State Circuits Conference.

[25]  E. Swanson,et al.  A monolithic 20 b delta-sigma A/D converter , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[26]  R. H. Walden,et al.  A 3.2-GHz second-order delta-sigma modulator implemented in InP HBT technology , 1995, IEEE J. Solid State Circuits.