A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon® processor

Nehalem-EX® is the most recent product in the family of the X86 Xeon microprocessors targeting high performance, low-power products [1, 2]. Several key design requirements for this product include high bandwidth, low-latency shared L3 cache access, design modularity to support efficient release of multiple products, and low power and silicon area overhead. A ring interconnect is particularly well suited to achieve all of these design requirements [3]. The implementation details for accomplishing the design target will be described in this paper.